?? lpc32x0.s
字號(hào):
LDR R0, =SYSTEM_BASE
; If PLL397 is used for system clock
IF (SYSCLK_CTRL_Val:AND:SYSCLK_PLL_BIT) != 0
PLL_Loop LDR R1, [R0, #PLL397_CTRL_OFS] ; Wait for PLL397 stabil
ANDS R1, R1, #PLL_LOCK_BIT
BEQ PLL_Loop
LDR R1, =SYSCLK_CTRL_Val ; Switch to PLL397
STR R1, [R0, #SYSCLK_CTRL_OFS]
LDR R1, =OSC_CTRL_Val ; Control main oscillator
STR R1, [R0, #OSC_CTRL_OFS]
ELSE ; If PLL397 is not used for system clock
LDR R1, =SYSCLK_CTRL_Val ; Control PLL397
STR R1, [R0, #SYSCLK_CTRL_OFS]
ENDIF
LDR R1, =HCLKPLL_CTRL_Val ; Setup HCLK PLL
STR R1, [R0, #HCLKPLL_CTRL_OFS]
; If HCLK PLL is setup for operating mode
IF (HCLKPLL_CTRL_Val:AND:HCLKPLL_PD_BIT) != 0
HCLK_Loop LDR R1, [R0, #HCLKPLL_CTRL_OFS] ; Wait for HCLK stabil
ANDS R1, R1, #PLL_LOCK_BIT
BEQ HCLK_Loop
LDR R1, =HCLKDIV_CTRL_Val ; Setup HCLK dividers
STR R1, [R0, #HCLKDIV_CTRL_OFS]
LDR R1, [R0, #PWR_CTRL_OFS] ; Switch to Normal RUN
ORR R1, R1, #NORMAL_RUN_BIT
STR R1, [R0, #PWR_CTRL_OFS]
ENDIF
ENDIF ;CLOCK_SETUP != 0
; EMC Setup --------------------------------------------------------------------
IF (:LNOT::DEF:EMC_NO_INIT):LAND:(EMC_SETUP != 0)
LDR R0, =SYSTEM_BASE ; Address of SYS CON Config
LDR R1, =EMC_BASE ; Address of EMC Controller
LDR R2, =DYN_MEM0_BASE ; External SDRAM0 Start Adr
LDR R3, =DYN_MEM1_BASE ; External SDRAM1 Start Adr
; Setup Dynamic Memory Interface
MOV R5, #0
MOV R4, #0x01 ; Enable SDRAM Controller
STR R4, [R1, #EMCControl_OFS]
LDR R4, =EMCConfig_Val
STR R4, [R1, #EMCConfig_OFS]
; Setup Dynamic Memory Interface
IF (:LNOT::DEF:EMC_DYNAMIC_NO_INIT):LAND:(EMC_DYNAMIC_SETUP != 0)
LDR R4, =SDRAMCLK_CTRL_Val
STR R4, [R1, #SDRAMCLK_CTRL_OFS]
LDR R4, =EMCDynRP_Val
STR R4, [R1, #EMCDynRP_OFS]
LDR R4, =EMCDynRAS_Val
STR R4, [R1, #EMCDynRAS_OFS]
LDR R4, =EMCDynSREX_Val
STR R4, [R1, #EMCDynSREX_OFS]
LDR R4, =EMCDynWR_Val
STR R4, [R1, #EMCDynWR_OFS]
LDR R4, =EMCDynRC_Val
STR R4, [R1, #EMCDynRC_OFS]
LDR R4, =EMCDynRFC_Val
STR R4, [R1, #EMCDynRFC_OFS]
LDR R4, =EMCDynXSR_Val
STR R4, [R1, #EMCDynXSR_OFS]
LDR R4, =EMCDynRRD_Val
STR R4, [R1, #EMCDynRRD_OFS]
LDR R4, =EMCDynMRD_Val
STR R4, [R1, #EMCDynMRD_OFS]
LDR R4, =EMCDynCDLR_Val
STR R4, [R1, #EMCDynCDLR_OFS]
LDR R4, =EMCDynReadCfg_Val
STR R4, [R1, #EMCDynReadCfg_OFS]
IF (EMC_DYNCS0_SETUP != 0)
LDR R4, =EMCDynRasCas0_Val
STR R4, [R1, #EMCDynRasCas0_OFS]
LDR R4, =EMCDynConfig0_Val
STR R4, [R1, #EMCDynConfig0_OFS]
ENDIF
IF (EMC_DYNCS1_SETUP != 0)
LDR R4, =EMCDynRasCas1_Val
STR R4, [R1, #EMCDynRasCas1_OFS]
LDR R4, =EMCDynConfig1_Val
STR R4, [R1, #EMCDynConfig1_OFS]
ENDIF
LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command
STR R4, [R1, #EMCDynControl_OFS]
LDR R6, =100*52 ; ~100us at 208 MHz
Wait_0 SUBS R6, R6, #1
BNE Wait_0
LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command
STR R4, [R1, #EMCDynControl_OFS]
LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command
STR R4, [R1, #EMCDynControl_OFS]
MOV R4, #2
STR R4, [R1, #EMCDynRefresh_OFS]
MOV R6, #1*52 ; ~1us at 208 MHz
Wait_1 SUBS R6, R6, #1
BNE Wait_1
LDR R4, =EMCDynRefresh_Val
STR R4, [R1, #EMCDynRefresh_OFS]
MOV R6, #1*52 ; ~1us at 208 MHz
Wait_2 SUBS R6, R6, #1
BNE Wait_2
LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command
STR R4, [R1, #EMCDynControl_OFS]
; Set memory mode (dummy read)
IF (EMC_DYNCS0_SETUP != 0)
LDR R4, =SDRAM0_MODE_REG
LDR R4, [R4, #0]
MOV R6, #1*52 ; ~1us at 208 MHz
Wait_3 SUBS R6, R6, #1
BNE Wait_3
LDR R4, =SDRAM0_EXT_MODE_REG
LDR R4, [R4, #0]
ENDIF
IF (EMC_DYNCS1_SETUP != 0)
LDR R4, =SDRAM1_MODE_REG
LDR R4, [R4, #0]
MOV R6, #1*52 ; ~1us at 208 MHz
Wait_4 SUBS R6, R6, #1
BNE Wait_4
LDR R4, =SDRAM1_EXT_MODE_REG
LDR R4, [R4, #0]
ENDIF
LDR R4, =NORMAL_CMD ; Write NORMAL Command
STR R4, [R1, #EMCDynControl_OFS]
MOV R6, #1*52 ; ~1us at 208 MHz
Wait_5 SUBS R6, R6, #1
BNE Wait_5
IF (EMC_DYNCS0_SETUP != 0)
IF (EMC_AHB0_SETUP != 0)
LDR R4, =EMCAHBControl0_Val
STR R4, [R1, #EMCAHBControl0_OFS]
LDR R4, =EMCAHBTimeOut0_Val ; AHB 0 Timeout
STR R4, [R1, #EMCAHBTimeOut0_OFS]
ENDIF
IF (EMC_AHB2_SETUP != 0)
LDR R4, =EMCAHBControl2_Val
STR R4, [R1, #EMCAHBControl2_OFS]
LDR R4, =EMCAHBTimeOut2_Val ; AHB 2 Timeout
STR R4, [R1, #EMCAHBTimeOut2_OFS]
ENDIF
IF (EMC_AHB3_SETUP != 0)
LDR R4, =EMCAHBControl3_Val
STR R4, [R1, #EMCAHBControl3_OFS]
LDR R4, =EMCAHBTimeOut3_Val ; AHB 3 Timeout
STR R4, [R1, #EMCAHBTimeOut3_OFS]
ENDIF
IF (EMC_AHB4_SETUP != 0)
LDR R4, =EMCAHBControl4_Val
STR R4, [R1, #EMCAHBControl4_OFS]
LDR R4, =EMCAHBTimeOut4_Val ; AHB 4 Timeout
STR R4, [R1, #EMCAHBTimeOut4_OFS]
ENDIF
ENDIF ;(EMC_DYNCS0_SETUP != 0)
ENDIF ;(:LNOT::DEF:EMC_DYNAMIC_NO_INIT):LAND:(EMC_DYNAMIC_SETUP != 0)
; Setup Static Memory Interface
IF (:LNOT::DEF:EMC_STATIC_NO_INIT):LAND:(EMC_STATIC_SETUP != 0)
IF (EMC_STACS0_SETUP != 0)
LDR R4, =EMCStaConfig0_Val
STR R4, [R0, #EMCStaConfig0_OFS]
LDR R4, =EMCStaWaitWen0_Val
STR R4, [R0, #EMCStaWaitWen0_OFS]
LDR R4, =EMCStaWaitOen0_Val
STR R4, [R0, #EMCStaWaitOen0_OFS]
LDR R4, =EMCStaWaitRd0_Val
STR R4, [R0, #EMCStaWaitRd0_OFS]
LDR R4, =EMCStaWaitPage0_Val
STR R4, [R0, #EMCStaWaitPage0_OFS]
LDR R4, =EMCStaWaitWr0_Val
STR R4, [R0, #EMCStaWaitWr0_OFS]
LDR R4, =EMCStaWaitTurn0_Val
STR R4, [R0, #EMCStaWaitTurn0_OFS]
ENDIF
IF (EMC_STACS1_SETUP != 0)
LDR R4, =EMCStaConfig1_Val
STR R4, [R0, #EMCStaConfig1_OFS]
LDR R4, =EMCStaWaitWen1_Val
STR R4, [R0, #EMCStaWaitWen1_OFS]
LDR R4, =EMCStaWaitOen1_Val
STR R4, [R0, #EMCStaWaitOen1_OFS]
LDR R4, =EMCStaWaitRd1_Val
STR R4, [R0, #EMCStaWaitRd1_OFS]
LDR R4, =EMCStaWaitPage1_Val
STR R4, [R0, #EMCStaWaitPage1_OFS]
LDR R4, =EMCStaWaitWr1_Val
STR R4, [R0, #EMCStaWaitWr1_OFS]
LDR R4, =EMCStaWaitTurn1_Val
STR R4, [R0, #EMCStaWaitTurn1_OFS]
ENDIF
IF (EMC_STACS2_SETUP != 0)
LDR R4, =EMCStaConfig2_Val
STR R4, [R0, #EMCStaConfig2_OFS]
LDR R4, =EMCStaWaitWen2_Val
STR R4, [R0, #EMCStaWaitWen2_OFS]
LDR R4, =EMCStaWaitOen2_Val
STR R4, [R0, #EMCStaWaitOen2_OFS]
LDR R4, =EMCStaWaitRd2_Val
STR R4, [R0, #EMCStaWaitRd2_OFS]
LDR R4, =EMCStaWaitPage2_Val
STR R4, [R0, #EMCStaWaitPage2_OFS]
LDR R4, =EMCStaWaitWr2_Val
STR R4, [R0, #EMCStaWaitWr2_OFS]
LDR R4, =EMCStaWaitTurn2_Val
STR R4, [R0, #EMCStaWaitTurn2_OFS]
ENDIF
IF (EMC_STACS3_SETUP != 0)
LDR R4, =EMCStaConfig3_Val
STR R4, [R0, #EMCStaConfig3_OFS]
LDR R4, =EMCStaWaitWen3_Val
LDR R4, =EMCStaWaitOen3_Val
STR R4, [R0, #EMCStaWaitOen3_OFS]
LDR R4, =EMCStaWaitRd3_Val
STR R4, [R0, #EMCStaWaitRd3_OFS]
LDR R4, =EMCStaWaitPage3_Val
STR R4, [R0, #EMCStaWaitPage3_OFS]
LDR R4, =EMCStaWaitWr3_Val
STR R4, [R0, #EMCStaWaitWr3_OFS]
LDR R4, =EMCStaWaitTurn3_Val
ENDIF
LDR R4, =EMCStaExtWait_Val
STR R4, [R0, #EMCStaExtWait_OFS]
ENDIF ;(:LNOT::DEF:EMC_STATIC_NO_INIT):LAND:(EMC_STATIC_SETUP != 0)
ENDIF ;(:LNOT::DEF:EMC_NO_INIT):LAND:(EMC_SETUP != 0)
; NAND Flash Setup -------------------------------------------------------------
IF (:LNOT::DEF:NAND_NO_INIT):LAND:(NANDC_SETUP != 0)
LDR R0, =SYSTEM_BASE ; Address of SYSTEM CONTROL Config
LDR R1, =MLC_BASE ; Address of MLC NAND Controller
LDR R2, =MLC_DATA_BASE ; Address of MLC Data Buffer
MOV R5, #0 ; 0 value
LDR R4, =FLASHCLK_CTRL_Val ; Setup NAND Flash Clock Control
STR R4, [R0, #FLASHCLK_CTRL_OFS]
LDR R4, =MLC_CEH_Val ; Setup NAND Flash Chip-Enable Control
STR R4, [R1, #MLC_CEH_OFS]
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