?? at91sam9261.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// Copyright (c) 2006, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the disclaimer below in the documentation and/or
// other materials provided with the distribution.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9261.h
// Object : AT91SAM9261 definitions
// Generated : AT91 SW Application Group 12/07/2006 (13:32:10)
//
// CVS Reference : /AT91SAM9261.pl/1.14/Mon Sep 4 16:48:03 2006//
// CVS Reference : /SYS_SAM9261.pl/1.5/Thu Nov 18 13:22:33 2004//
// CVS Reference : /HMATRIX1_SAM9261.pl/1.2/Mon Nov 8 16:38:17 2004//
// CVS Reference : /PMC_SAM9261.pl/1.4/Fri Sep 9 15:24:01 2005//
// CVS Reference : /HSMC3_SAM9261.pl/1.1/Tue Nov 16 09:16:07 2004//
// CVS Reference : /SHDWC_SAM9261.pl/1.1/Tue Mar 8 14:46:52 2005//
// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006//
// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
// CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
// CVS Reference : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004//
// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006//
// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
// CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
// CVS Reference : /LCDC_6063A.pl/1.3/Fri Dec 9 10:59:26 2005//
// ----------------------------------------------------------------------------
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
#ifndef __ASSEMBLY__
typedef volatile unsigned int AT91_REG;// Hardware register definition
#define AT91_CAST(a) (a)
#else
#define AT91_CAST(a)
#endif
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
#ifndef __ASSEMBLY__
typedef struct _AT91S_SYS {
AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
AT91_REG Reserved0[118]; //
AT91_REG SMC_SETUP0; // Setup Register for CS 0
AT91_REG SMC_PULSE0; // Pulse Register for CS 0
AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
AT91_REG SMC_CTRL0; // Control Register for CS 0
AT91_REG SMC_SETUP1; // Setup Register for CS 1
AT91_REG SMC_PULSE1; // Pulse Register for CS 1
AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
AT91_REG SMC_CTRL1; // Control Register for CS 1
AT91_REG SMC_SETUP2; // Setup Register for CS 2
AT91_REG SMC_PULSE2; // Pulse Register for CS 2
AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
AT91_REG SMC_CTRL2; // Control Register for CS 2
AT91_REG SMC_SETUP3; // Setup Register for CS 3
AT91_REG SMC_PULSE3; // Pulse Register for CS 3
AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
AT91_REG SMC_CTRL3; // Control Register for CS 3
AT91_REG SMC_SETUP4; // Setup Register for CS 4
AT91_REG SMC_PULSE4; // Pulse Register for CS 4
AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
AT91_REG SMC_CTRL4; // Control Register for CS 4
AT91_REG SMC_SETUP5; // Setup Register for CS 5
AT91_REG SMC_PULSE5; // Pulse Register for CS 5
AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
AT91_REG SMC_CTRL5; // Control Register for CS 5
AT91_REG SMC_SETUP6; // Setup Register for CS 6
AT91_REG SMC_PULSE6; // Pulse Register for CS 6
AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
AT91_REG SMC_CTRL6; // Control Register for CS 6
AT91_REG SMC_SETUP7; // Setup Register for CS 7
AT91_REG SMC_PULSE7; // Pulse Register for CS 7
AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
AT91_REG SMC_CTRL7; // Control Register for CS 7
AT91_REG Reserved1[96]; //
AT91_REG MATRIX_MCFG; // Master Configuration Register
AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
AT91_REG Reserved2[3]; //
AT91_REG MATRIX_TCMR; // Slave 0 Special Function Register
AT91_REG Reserved3[2]; //
AT91_REG MATRIX_EBICSA; // Slave 3 Special Function Register
AT91_REG MATRIX_USBPCR; // Slave 4 Special Function Register
AT91_REG Reserved4[3]; //
AT91_REG MATRIX_VERSION; // Version Register
AT91_REG Reserved5[110]; //
AT91_REG AIC_SMR[32]; // Source Mode Register
AT91_REG AIC_SVR[32]; // Source Vector Register
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved6[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command Register
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
AT91_REG AIC_DCR; // Debug Control Register (Protect)
AT91_REG Reserved7[1]; //
AT91_REG AIC_FFER; // Fast Forcing Enable Register
AT91_REG AIC_FFDR; // Fast Forcing Disable Register
AT91_REG AIC_FFSR; // Fast Forcing Status Register
AT91_REG Reserved8[45]; //
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved9[7]; //
AT91_REG DBGU_CIDR; // Chip ID Register
AT91_REG DBGU_EXID; // Chip ID Extension Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved10[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
AT91_REG Reserved11[54]; //
AT91_REG PIOA_PER; // PIO Enable Register
AT91_REG PIOA_PDR; // PIO Disable Register
AT91_REG PIOA_PSR; // PIO Status Register
AT91_REG Reserved12[1]; //
AT91_REG PIOA_OER; // Output Enable Register
AT91_REG PIOA_ODR; // Output Disable Registerr
AT91_REG PIOA_OSR; // Output Status Register
AT91_REG Reserved13[1]; //
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