?? at91sam7a3.tcl
字號:
set AT91C_TC_BURST_NONE [expr 0x0 << 4 ]
set AT91C_TC_BURST_XC0 [expr 0x1 << 4 ]
set AT91C_TC_BURST_XC1 [expr 0x2 << 4 ]
set AT91C_TC_BURST_XC2 [expr 0x3 << 4 ]
set AT91C_TC_CPCSTOP [expr 0x1 << 6 ]
set AT91C_TC_LDBSTOP [expr 0x1 << 6 ]
set AT91C_TC_CPCDIS [expr 0x1 << 7 ]
set AT91C_TC_LDBDIS [expr 0x1 << 7 ]
set AT91C_TC_ETRGEDG [expr 0x3 << 8 ]
set AT91C_TC_ETRGEDG_NONE [expr 0x0 << 8 ]
set AT91C_TC_ETRGEDG_RISING [expr 0x1 << 8 ]
set AT91C_TC_ETRGEDG_FALLING [expr 0x2 << 8 ]
set AT91C_TC_ETRGEDG_BOTH [expr 0x3 << 8 ]
set AT91C_TC_EEVTEDG [expr 0x3 << 8 ]
set AT91C_TC_EEVTEDG_NONE [expr 0x0 << 8 ]
set AT91C_TC_EEVTEDG_RISING [expr 0x1 << 8 ]
set AT91C_TC_EEVTEDG_FALLING [expr 0x2 << 8 ]
set AT91C_TC_EEVTEDG_BOTH [expr 0x3 << 8 ]
set AT91C_TC_EEVT [expr 0x3 << 10 ]
set AT91C_TC_EEVT_TIOB [expr 0x0 << 10 ]
set AT91C_TC_EEVT_XC0 [expr 0x1 << 10 ]
set AT91C_TC_EEVT_XC1 [expr 0x2 << 10 ]
set AT91C_TC_EEVT_XC2 [expr 0x3 << 10 ]
set AT91C_TC_ABETRG [expr 0x1 << 10 ]
set AT91C_TC_ENETRG [expr 0x1 << 12 ]
set AT91C_TC_WAVESEL [expr 0x3 << 13 ]
set AT91C_TC_WAVESEL_UP [expr 0x0 << 13 ]
set AT91C_TC_WAVESEL_UPDOWN [expr 0x1 << 13 ]
set AT91C_TC_WAVESEL_UP_AUTO [expr 0x2 << 13 ]
set AT91C_TC_WAVESEL_UPDOWN_AUTO [expr 0x3 << 13 ]
set AT91C_TC_CPCTRG [expr 0x1 << 14 ]
set AT91C_TC_WAVE [expr 0x1 << 15 ]
set AT91C_TC_WAVE [expr 0x1 << 15 ]
set AT91C_TC_ACPA [expr 0x3 << 16 ]
set AT91C_TC_ACPA_NONE [expr 0x0 << 16 ]
set AT91C_TC_ACPA_SET [expr 0x1 << 16 ]
set AT91C_TC_ACPA_CLEAR [expr 0x2 << 16 ]
set AT91C_TC_ACPA_TOGGLE [expr 0x3 << 16 ]
set AT91C_TC_LDRA [expr 0x3 << 16 ]
set AT91C_TC_LDRA_NONE [expr 0x0 << 16 ]
set AT91C_TC_LDRA_RISING [expr 0x1 << 16 ]
set AT91C_TC_LDRA_FALLING [expr 0x2 << 16 ]
set AT91C_TC_LDRA_BOTH [expr 0x3 << 16 ]
set AT91C_TC_ACPC [expr 0x3 << 18 ]
set AT91C_TC_ACPC_NONE [expr 0x0 << 18 ]
set AT91C_TC_ACPC_SET [expr 0x1 << 18 ]
set AT91C_TC_ACPC_CLEAR [expr 0x2 << 18 ]
set AT91C_TC_ACPC_TOGGLE [expr 0x3 << 18 ]
set AT91C_TC_LDRB [expr 0x3 << 18 ]
set AT91C_TC_LDRB_NONE [expr 0x0 << 18 ]
set AT91C_TC_LDRB_RISING [expr 0x1 << 18 ]
set AT91C_TC_LDRB_FALLING [expr 0x2 << 18 ]
set AT91C_TC_LDRB_BOTH [expr 0x3 << 18 ]
set AT91C_TC_AEEVT [expr 0x3 << 20 ]
set AT91C_TC_AEEVT_NONE [expr 0x0 << 20 ]
set AT91C_TC_AEEVT_SET [expr 0x1 << 20 ]
set AT91C_TC_AEEVT_CLEAR [expr 0x2 << 20 ]
set AT91C_TC_AEEVT_TOGGLE [expr 0x3 << 20 ]
set AT91C_TC_ASWTRG [expr 0x3 << 22 ]
set AT91C_TC_ASWTRG_NONE [expr 0x0 << 22 ]
set AT91C_TC_ASWTRG_SET [expr 0x1 << 22 ]
set AT91C_TC_ASWTRG_CLEAR [expr 0x2 << 22 ]
set AT91C_TC_ASWTRG_TOGGLE [expr 0x3 << 22 ]
set AT91C_TC_BCPB [expr 0x3 << 24 ]
set AT91C_TC_BCPB_NONE [expr 0x0 << 24 ]
set AT91C_TC_BCPB_SET [expr 0x1 << 24 ]
set AT91C_TC_BCPB_CLEAR [expr 0x2 << 24 ]
set AT91C_TC_BCPB_TOGGLE [expr 0x3 << 24 ]
set AT91C_TC_BCPC [expr 0x3 << 26 ]
set AT91C_TC_BCPC_NONE [expr 0x0 << 26 ]
set AT91C_TC_BCPC_SET [expr 0x1 << 26 ]
set AT91C_TC_BCPC_CLEAR [expr 0x2 << 26 ]
set AT91C_TC_BCPC_TOGGLE [expr 0x3 << 26 ]
set AT91C_TC_BEEVT [expr 0x3 << 28 ]
set AT91C_TC_BEEVT_NONE [expr 0x0 << 28 ]
set AT91C_TC_BEEVT_SET [expr 0x1 << 28 ]
set AT91C_TC_BEEVT_CLEAR [expr 0x2 << 28 ]
set AT91C_TC_BEEVT_TOGGLE [expr 0x3 << 28 ]
set AT91C_TC_BSWTRG [expr 0x3 << 30 ]
set AT91C_TC_BSWTRG_NONE [expr 0x0 << 30 ]
set AT91C_TC_BSWTRG_SET [expr 0x1 << 30 ]
set AT91C_TC_BSWTRG_CLEAR [expr 0x2 << 30 ]
set AT91C_TC_BSWTRG_TOGGLE [expr 0x3 << 30 ]
# -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
set AT91C_TC_CLKSTA [expr 0x1 << 16 ]
set AT91C_TC_MTIOA [expr 0x1 << 17 ]
set AT91C_TC_MTIOB [expr 0x1 << 18 ]
# -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
# -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
# -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
set AT91C_TC_COVFS [expr 0x1 << 0 ]
set AT91C_TC_LOVRS [expr 0x1 << 1 ]
set AT91C_TC_CPAS [expr 0x1 << 2 ]
set AT91C_TC_CPBS [expr 0x1 << 3 ]
set AT91C_TC_CPCS [expr 0x1 << 4 ]
set AT91C_TC_LDRAS [expr 0x1 << 5 ]
set AT91C_TC_LDRBS [expr 0x1 << 6 ]
set AT91C_TC_ETRGS [expr 0x1 << 7 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Timer Counter Interface
# *****************************************************************************
# -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
set AT91C_TCB_SYNC [expr 0x1 << 0 ]
# -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
set AT91C_TCB_TC0XC0S [expr 0x3 << 0 ]
set AT91C_TCB_TC0XC0S_TCLK0 0x0
set AT91C_TCB_TC0XC0S_NONE 0x1
set AT91C_TCB_TC0XC0S_TIOA1 0x2
set AT91C_TCB_TC0XC0S_TIOA2 0x3
set AT91C_TCB_TC1XC1S [expr 0x3 << 2 ]
set AT91C_TCB_TC1XC1S_TCLK1 [expr 0x0 << 2 ]
set AT91C_TCB_TC1XC1S_NONE [expr 0x1 << 2 ]
set AT91C_TCB_TC1XC1S_TIOA0 [expr 0x2 << 2 ]
set AT91C_TCB_TC1XC1S_TIOA2 [expr 0x3 << 2 ]
set AT91C_TCB_TC2XC2S [expr 0x3 << 4 ]
set AT91C_TCB_TC2XC2S_TCLK2 [expr 0x0 << 4 ]
set AT91C_TCB_TC2XC2S_NONE [expr 0x1 << 4 ]
set AT91C_TCB_TC2XC2S_TIOA0 [expr 0x2 << 4 ]
set AT91C_TCB_TC2XC2S_TIOA1 [expr 0x3 << 4 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Multimedia Card Interface
# *****************************************************************************
# -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
set AT91C_MCI_MCIEN [expr 0x1 << 0 ]
set AT91C_MCI_MCIDIS [expr 0x1 << 1 ]
set AT91C_MCI_PWSEN [expr 0x1 << 2 ]
set AT91C_MCI_PWSDIS [expr 0x1 << 3 ]
set AT91C_MCI_SWRST [expr 0x1 << 7 ]
# -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
set AT91C_MCI_CLKDIV [expr 0xFF << 0 ]
set AT91C_MCI_PWSDIV [expr 0x7 << 8 ]
set AT91C_MCI_PDCPADV [expr 0x1 << 14 ]
set AT91C_MCI_PDCMODE [expr 0x1 << 15 ]
set AT91C_MCI_BLKLEN [expr 0xFFF << 18 ]
# -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
set AT91C_MCI_DTOCYC [expr 0xF << 0 ]
set AT91C_MCI_DTOMUL [expr 0x7 << 4 ]
set AT91C_MCI_DTOMUL_1 [expr 0x0 << 4 ]
set AT91C_MCI_DTOMUL_16 [expr 0x1 << 4 ]
set AT91C_MCI_DTOMUL_128 [expr 0x2 << 4 ]
set AT91C_MCI_DTOMUL_256 [expr 0x3 << 4 ]
set AT91C_MCI_DTOMUL_1024 [expr 0x4 << 4 ]
set AT91C_MCI_DTOMUL_4096 [expr 0x5 << 4 ]
set AT91C_MCI_DTOMUL_65536 [expr 0x6 << 4 ]
set AT91C_MCI_DTOMUL_1048576 [expr 0x7 << 4 ]
# -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
set AT91C_MCI_SCDSEL [expr 0xF << 0 ]
set AT91C_MCI_SCDBUS [expr 0x1 << 7 ]
# -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
set AT91C_MCI_CMDNB [expr 0x3F << 0 ]
set AT91C_MCI_RSPTYP [expr 0x3 << 6 ]
set AT91C_MCI_RSPTYP_NO [expr 0x0 << 6 ]
set AT91C_MCI_RSPTYP_48 [expr 0x1 << 6 ]
set AT91C_MCI_RSPTYP_136 [expr 0x2 << 6 ]
set AT91C_MCI_SPCMD [expr 0x7 << 8 ]
set AT91C_MCI_SPCMD_NONE [expr 0x0 << 8 ]
set AT91C_MCI_SPCMD_INIT [expr 0x1 << 8 ]
set AT91C_MCI_SPCMD_SYNC [expr 0x2 << 8 ]
set AT91C_MCI_SPCMD_IT_CMD [expr 0x4 << 8 ]
set AT91C_MCI_SPCMD_IT_REP [expr 0x5 << 8 ]
set AT91C_MCI_OPDCMD [expr 0x1 << 11 ]
set AT91C_MCI_MAXLAT [expr 0x1 << 12 ]
set AT91C_MCI_TRCMD [expr 0x3 << 16 ]
set AT91C_MCI_TRCMD_NO [expr 0x0 << 16 ]
set AT91C_MCI_TRCMD_START [expr 0x1 << 16 ]
set AT91C_MCI_TRCMD_STOP [expr 0x2 << 16 ]
set AT91C_MCI_TRDIR [expr 0x1 << 18 ]
set AT91C_MCI_TRTYP [expr 0x3 << 19 ]
set AT91C_MCI_TRTYP_BLOCK [expr 0x0 << 19 ]
set AT91C_MCI_TRTYP_MULTIPLE [expr 0x1 << 19 ]
set AT91C_MCI_TRTYP_STREAM [expr 0x2 << 19 ]
# -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
set AT91C_MCI_CMDRDY [expr 0x1 << 0 ]
set AT91C_MCI_RXRDY [expr 0x1 << 1 ]
set AT91C_MCI_TXRDY [expr 0x1 << 2 ]
set AT91C_MCI_BLKE [expr 0x1 << 3 ]
set AT91C_MCI_DTIP [expr 0x1 << 4 ]
set AT91C_MCI_NOTBUSY [expr 0x1 << 5 ]
set AT91C_MCI_ENDRX [expr 0x1 << 6 ]
set AT91C_MCI_ENDTX [expr 0x1 << 7 ]
set AT91C_MCI_RXBUFF [expr 0x1 << 14 ]
set AT91C_MCI_TXBUFE [expr 0x1 << 15 ]
set AT91C_MCI_RINDE [expr 0x1 << 16 ]
set AT91C_MCI_RDIRE [expr 0x1 << 17 ]
set AT91C_MCI_RCRCE [expr 0x1 << 18 ]
set AT91C_MCI_RENDE [expr 0x1 << 19 ]
set AT91C_MCI_RTOE [expr 0x1 << 20 ]
set AT91C_MCI_DCRCE [expr 0x1 << 21 ]
set AT91C_MCI_DTOE [expr 0x1 << 22 ]
set AT91C_MCI_OVRE [expr 0x1 << 30 ]
set AT91C_MCI_UNRE [expr 0x1 << 31 ]
# -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
set AT91C_MCI_CMDRDY [expr 0x1 << 0 ]
set AT91C_MCI_RXRDY [expr 0x1 << 1 ]
set AT91C_MCI_TXRDY [expr 0x1 << 2 ]
set AT91C_MCI_BLKE [expr 0x1 << 3 ]
set AT91C_MCI_DTIP [expr 0x1 << 4 ]
set AT91C_MCI_NOTBUSY [expr 0x1 << 5 ]
set AT91C_MCI_ENDRX [expr 0x1 << 6 ]
set AT91C_MCI_ENDTX [expr 0x1 << 7 ]
set AT91C_MCI_RXBUFF [expr 0x1 << 14 ]
set AT91C_MCI_TXBUFE [expr 0x1 << 15 ]
set AT91C_MCI_RINDE [expr 0x1 << 16 ]
set AT91C_MCI_RDIRE [expr 0x1 << 17 ]
set AT91C_MCI_RCRCE [expr 0x1 << 18 ]
set AT91C_MCI_RENDE [expr 0x1 << 19 ]
set AT91C_MCI_RTOE [expr 0x1 << 20 ]
set AT91C_MCI_DCRCE [expr 0x1 << 21 ]
set AT91C_MCI_DTOE [expr 0x1 << 22 ]
set AT91C_MCI_OVRE [expr 0x1 << 30 ]
set AT91C_MCI_UNRE [expr 0x1 << 31 ]
# -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
set AT91C_MCI_CMDRDY [expr 0x1 << 0 ]
set AT91C_MCI_RXRDY [expr 0x1 << 1 ]
set AT91C_MCI_TXRDY [expr 0x1 << 2 ]
set AT91C_MCI_BLKE [expr 0x1 << 3 ]
set AT91C_MCI_DTIP [expr 0x1 << 4 ]
set AT91C_MCI_NOTBUSY [expr 0x1 << 5 ]
set AT91C_MCI_ENDRX [expr 0x1 << 6 ]
set AT91C_MCI_ENDTX [expr 0x1 << 7 ]
set AT91C_MCI_RXBUFF [expr 0x1 << 14 ]
set AT91C_MCI_TXBUFE [expr 0x1 << 15 ]
set AT91C_MCI_RINDE [expr 0x1 << 16 ]
set AT91C_MCI_RDIRE [expr 0x1 << 17 ]
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