?? sam7_ram.mac
字號(hào):
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM7_RAM.mac
//
// 1.0 08/Mar/05 JPP : Creation
// 1.1 23/Mar/05 JPP : Change Variable name
//
// $Revision: 1.2 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;
__var __mac_mem;
execUserReset()
{
CheckNoRemap();
ini();
AIC();
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0x00000000,0xB4,"Register");
}
execUserPreload()
{
//* __message "-------------------------------Set CPSR ----------------------------------";
__writeMemory32(0xD3,0x98,"Register");
__writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
PllSetting();
//* Init AIC
AIC();
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
CheckNoRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
__mac_i=__readMemory32(0xFFFFF244,"Memory");
__message " ---------------------------------------- Extention 0x",__mac_i:%X;
__mac_i=__readMemory32(0xFFFFFF6C,"Memory");
__message " ---------------------------------------- Flash Version 0x",__mac_i:%X;
//* Watchdog Disable
Watchdog();
//* RG();
}
//-----------------------------------------------------------------------------
// PllSetting
//-------------------------------
// Set PLL
//-----------------------------------------------------------------------------
PllSetting()
{
// -1- Enabling the Main Oscillator:
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
// AT91C_CKGR_MOSCEN )); //0x0000 0001
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
// -2- Wait
// -3- Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
// Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
// -2- Wait
// -5- Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
__message "------------------------------- PLL Enable ----------------------------------------";
}
//-----------------------------------------------------------------------------
// Watchdog
//-------------------------------
// Normally, the Watchdog is enable at the reset for load it's preferable to
// Disable.
//-----------------------------------------------------------------------------
Watchdog()
{
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__message "------------------------------- Watchdog Disable ----------------------------------------";
}
CheckNoRemap()
{
//* Read the value at 0x0
__mac_i =__readMemory32(0x00000000,"Memory");
__mac_mem = __mac_i;
__mac_i=__mac_i+1;
__writeMemory32(__mac_i,0x00,"Memory");
__mac_pt=__readMemory32(0x00000000,"Memory");
if (__mac_i == __mac_pt)
{
__message "------------------------------- The Remap is done ----------------------------------------";
__writeMemory32( __mac_mem,0x00000000,"Memory");
} else {
__message "------------------------------- The Remap is NOT -----------------------------------------";
//* Toggel RESET The remap
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
}
}
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
// Normally, the code is executed only if a reset has been actually performed.
// So, the AIC initialization resumes at setting up the default vectors.
//-----------------------------------------------------------------------------
AIC()
{
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
__writeMemory32(0xffffffff,0xFFFFF124,"Memory");
__writeMemory32(0xffffffff,0xFFFFF128,"Memory");
// disable peripheral clock Peripheral Clock Disable Register
__writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// #define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register
// #define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register
// #define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register
// #define AT91C_TC6_SR ((AT91_REG *) 0xFFFA8020) // (TC6) Status Register
// #define AT91C_TC7_SR ((AT91_REG *) 0xFFFA8060) // (TC7) Status Register
// #define AT91C_TC8_SR ((AT91_REG *) 0xFFFA80A0) // (TC8) Status Register
__readMemory32(0xFFFA0020,"Memory");
__readMemory32(0xFFFA0060,"Memory");
__readMemory32(0xFFFA00A0,"Memory");
__readMemory32(0xFFFA4020,"Memory");
__readMemory32(0xFFFA4060,"Memory");
__readMemory32(0xFFFA40A0,"Memory");
__readMemory32(0xFFFA8020,"Memory");
__readMemory32(0xFFFA8060,"Memory");
__readMemory32(0xFFFA80A0,"Memory");
for (__mac_i=0;__mac_i < 8; __mac_i++)
{
// AT91C_BASE_AIC->AIC_EOICR
__mac_pt = __readMemory32(0xFFFFF130,"Memory");
}
__message "------------------------------- AIC 2 INIT ---------------------------------------------";
}
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
RG()
{
__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X;
__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X;
__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X;
__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X;
__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X;
__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X;
__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X;
__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X;
__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X;
__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X;
__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X;
__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X;
__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X;
__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X;
__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X;
__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X;
__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X;
__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X;
__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X;
__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X;
__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X;
__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X;
__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X;
__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X;
__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X;
__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X;
__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X;
__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X;
__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X;
__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X;
__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X;
}
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