?? at91sam7a3_inc.h
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#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Control Area Network Interface
// *****************************************************************************
// *** Register offset in AT91S_CAN structure ***
#define CAN_MR ( 0) // Mode Register
#define CAN_IER ( 4) // Interrupt Enable Register
#define CAN_IDR ( 8) // Interrupt Disable Register
#define CAN_IMR (12) // Interrupt Mask Register
#define CAN_SR (16) // Status Register
#define CAN_BR (20) // Baudrate Register
#define CAN_TIM (24) // Timer Register
#define CAN_TIMESTP (28) // Time Stamp Register
#define CAN_ECR (32) // Error Counter Register
#define CAN_TCR (36) // Transfer Command Register
#define CAN_ACR (40) // Abort Command Register
#define CAN_VR (252) // Version Register
#define CAN_MB0 (512) // CAN Mailbox 0
#define CAN_MB1 (544) // CAN Mailbox 1
#define CAN_MB2 (576) // CAN Mailbox 2
#define CAN_MB3 (608) // CAN Mailbox 3
#define CAN_MB4 (640) // CAN Mailbox 4
#define CAN_MB5 (672) // CAN Mailbox 5
#define CAN_MB6 (704) // CAN Mailbox 6
#define CAN_MB7 (736) // CAN Mailbox 7
#define CAN_MB8 (768) // CAN Mailbox 8
#define CAN_MB9 (800) // CAN Mailbox 9
#define CAN_MB10 (832) // CAN Mailbox 10
#define CAN_MB11 (864) // CAN Mailbox 11
#define CAN_MB12 (896) // CAN Mailbox 12
#define CAN_MB13 (928) // CAN Mailbox 13
#define CAN_MB14 (960) // CAN Mailbox 14
#define CAN_MB15 (992) // CAN Mailbox 15
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_TC structure ***
#define TC_CCR ( 0) // Channel Control Register
#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
#define TC_CV (16) // Counter Value
#define TC_RA (20) // Register A
#define TC_RB (24) // Register B
#define TC_RC (28) // Register C
#define TC_SR (32) // Status Register
#define TC_IER (36) // Interrupt Enable Register
#define TC_IDR (40) // Interrupt Disable Register
#define TC_IMR (44) // Interrupt Mask Register
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
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