#$Id: //depot/sw/branches/ART_V48/bringup/ar5k/config/ar5001x2_cb21g.eep#1 $

#EEPROM file for AR5001X+ 802.11b/g CardBus Revised Reference (new layout)

@cal_section_begin                  	# begin @cal section

TARGET_POWER_FILENAME      =  calTrgtPwr_ar5001x2_cb21g.txt; # target power file for calibration
SUBSYSTEM_ID	           =  0x1025;   # Subsystem ID in hex
TURBO_DISABLE		   =  0;        # Prevents software from using TURBO modes in 11a
RF_SILENT		   =  0;        # Cards enabled with RFSilent can be easily silenced
DEVICE_TYPE		   =  1;        # 1=>Cardbus, 2=>PCI, 3=>miniPCI, 4=>AP
TURBO_MAXPOWER_5G	   =  0;        # Recommended max power in turbo mode to consume less than 2W.
TURBO_MAXPOWER_2p5G	   =  16.0;   	# Recommended max power in turbo mode at 2.5 GHz to consume less than 2W.
A_MODE		           =  0;        # Whether the adapter supports 802.11a functionality
B_MODE		           =  1;        # Whether the adapter supports 802.11b functionality
G_MODE		           =  1;        # Whether the adapter supports 802.11g functionality
ANTENNA_GAIN_5G	           =  0;	# Antenna gain at 5GHz. 8-bit signed val in 0.5dB steps.
ANTENNA_GAIN_2p5G          =  1;        # Antenna gain at 2.5GHz. 8-bit signed val in 0.5dB steps.
XLNA_GAIN		   =  0;        # xLNA gain in dB (per AS 6/14/02)
NOISE_FLOOR_THRESHOLD	   = -1;        # noise floor threshold value (per JHfmn 6/14/02)
11b_XLNA_GAIN		   =  13;       # xLNA gain in dB
11b_NOISE_FLOOR_THRESHOLD  = -1;   	# noise floor threshold value
11g_XLNA_GAIN		   =  13;       # xLNA gain in dB
11g_NOISE_FLOOR_THRESHOLD  = -1;   	# noise floor threshold value
11a_FALSE_DETECT_BACKOFF   =  0;	# in dB. only affects channels w/ clock harmonic overlap.
11b_FALSE_DETECT_BACKOFF   =  0;	# in dB. only affects channels w/ clock harmonic overlap.
11g_FALSE_DETECT_BACKOFF   =  0;	# in dB. only affects channels w/ clock harmonic overlap.
11g_TURBO_DISABLE          =  0;        # Set to 1 to disable TURBO mode in 11g
11g_TURBO_DISABLE          =  0;        # Set to 1 to disable TURBO mode in 11g
CCK_OFDM_DELTA		   = 1.5;	# in dB with 0.1dB resolution. In 11g, delta in output power for 1mbps and 6mbps
					# for any given pcdac.
CH14_FILTER_CCK_DELTA	   =  1.5;	# in dB with 0.1dB resolution. In 11g & 11b, delta in output power for ch14 and ch1 - ch13
					# for any given pcdac. This delta arises due to special filter requirement for ch14 (2484).

@cal_section_end                    	# end @cal section	


@config_section_begin               	# begin @config section

#Antenna Switch Table
#6 bit (msb:lsb) value are mapped to [atten5, atten2, antD, antC, antB, antA]	            	
#----------------------------------------------------------------------------------
@MODE: MODE_SPECIFIC             11a   11a_turbo        11b         11g   11g_turbo
#----------------------------------------------------------------------------------
bb_switch_table_r1x12           0x00        0x00        0x20       0x20     0x20 #(AntCtl 5)
bb_switch_table_r1x2            0x00        0x00        0x10       0x10     0x10 #(AntCtl 4)
bb_switch_table_r1x1            0x00        0x00        0x2a       0x2a     0x2a #(AntCtl 3)
bb_switch_table_r1              0x00        0x00        0x1a       0x1a     0x1a #(AntCtl 2)
bb_switch_table_t1              0x00        0x00        0x25       0x25     0x25 #(AntCtl 1)

bb_switch_table_r2x12           0x00        0x00        0x20       0x20     0x20 #(AntCtl 10)
bb_switch_table_r2x2            0x00        0x00        0x10       0x10     0x10 #(AntCtl 9)
bb_switch_table_r2x1            0x00        0x00        0x25       0x25     0x25 #(AntCtl 8)
bb_switch_table_r2              0x00        0x00        0x15       0x15     0x15 #(AntCtl 7)
bb_switch_table_t2              0x00        0x00        0x2a       0x2a     0x2a #(AntCtl 6)

bb_rxtx_margin_2ghz               11          11          16         16         16
bb_switch_settling              0x00        0x00        0x2d       0x2d     0x5a
bb_txrxatten                    0x00        0x00          15         15       15
bb_pga_desired_size             0x00        0x00         -80        -80      -80
bb_adc_desired_size             0x00        0x00         -38        -32      -32
rf_b_ob                         0x00        0x00           4          3        3
rf_b_db                         0x00        0x00           4          3        3
rf_ob                           0x00        0x00           2          2        2
rf_db                           0x00        0x00           2          2        2 
rf_plo_sel                      0x00        0x00           1          1        1
rf_pwdxpd                       0x00        0x00           0          0        0
rf_xpd_gain	                0x00	    0x00	 0xb	    0xb      0xb
bb_thresh62		        0x00	    0x00	  28	     28       28
bb_tx_end_to_xpab_off           0x00        0x00           0          0        0
bb_tx_end_to_xpaa_off           0x00        0x00           0          0        0
bb_tx_frame_to_xpab_on 	    	0x00        0x00         0x7        0xe      0xe
bb_tx_frame_to_xpaa_on	    	0x00        0x00         0x7        0xe      0xe
bb_tx_end_to_xlna_on            0x00        0x00           2          2        2

rf_gain_I                       0x0a        0x0a        0x0a       0x0a     0x0a

@config_section_end                 # end @config section