?? boot.lis
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0073 VREGCR: equ 73h ; VREG Configuration Register (RW)
0000
0000 ; USB Transceiver Configuration Registers
0074 USBXCR: equ 74h ; USB Transceiver Configuration Register (RW)
0080 USBXCR_ENABLE: equ 80h ; USB Transceiver Enable
0001 USBXCR_FORCE: equ 01h ; USB Transceiver Force
0000
0000 ; Data Pointer Registers--Listed for compatability with other M8C based parts.
00D0 CPPDR: equ D0h ; Current Page Pointer Data Register (RW)
00D4 DPRDR: equ D4h ; Data Page Read Register (RW)
00D5 DPWDR: equ D5h ; Data Page Write Register (RW)
0000
0000 ; Watchdog Timer Reset
00E3 RESWDT: equ E3h ; Watchdog Timer Reset (W)
00E3 RES_WDT: equ E3h ; WatchDog Timer Register (W) (PSoC)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DC INT_CLR2: equ DCh ; Interrupt Clear Register 2 (RW)
0000 ; Use INT_MSK2 bit field masks
0000
00DE INT_MSK3: equ DEh ; Interrupt Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0000
00DF INT_MSK2: equ DFh ; Interrupt Mask Register (RW)
0040 INT_MSK2_GPIO_PORT4: equ 40h ; MASK: enable/disable GPIO Port 4 interrupt
0020 INT_MSK2_GPIO_PORT3: equ 20h ; MASK: enable/disable GPIO Port 3 interrupt
0010 INT_MSK2_GPIO_PORT2: equ 10h ; MASK: enable/disable GPIO Port 2 interrupt
0008 INT_MSK2_PS2_DATA_LOW: equ 08h ; MASK: enable/disable PS/2 Data Low
0004 INT_MSK2_GPIO_INT2: equ 04h ; MASK: enable/disable GPIO INT2 interrupt
0002 INT_MSK2_CTR_16_WRAP: equ 02h ; MASK: enable/disable 16 bit counter wrap
0001 INT_MSK2_TCAP1: equ 01h ; MASK: enable/disable Timer/Capture 0 interrupt
0000
00E0 INT_MSK0: equ E0h ; Interrupt Mask Register (RW)
0080 INT_MSK0_GPIO_PORT1: equ 80h ; MASK: enable/disable GPIO Port 1 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO_INT1: equ 20h ; MASK: enable/disable GPIO INT1 interrupt
0010 INT_MSK0_GPIO_PORT0: equ 10h ; MASK: enable/disable GPIO Port 0 interrupt
0008 INT_MSK0_SPI_RX: equ 08h ; MASK: enable/disable SPI Receive interrupt
0004 INT_MSK0_SPI_TX: equ 04h ; MASK: enable/disable SPI Transmit interrupt
0002 INT_MSK0_GPIO_INT0: equ 02h ; MASK: enable/disable GPIO INT0 interrupt
0001 INT_MSK0_POR_LVD: equ 01h ; MASK: enable/disable POR/LVD interrupt
0000
00E1 INT_MSK1: equ E1h ; Interrupt Mask Register (RW)
0080 INT_MSK1_TCAP0: equ 80h ; MASK: enable/disable Timer/Capture 0 interrupt
0040 INT_MSK1_PIT: equ 40h ; MASK: enable/disable Progrmmable Interval Timer
0020 INT_MSK1_MS_TIMER: equ 20h ; MASK: enable/disable One Millisecond Timer interrupt
0010 INT_MSK1_USB_ACTIVITY: equ 10h ; MASK: enable/disable USB Bus Activity interrupt
0008 INT_MSK1_USB_BUS_RESET: equ 08h ; MASK: enable/disable USB Bus Reset interrupt
0004 INT_MSK1_USB_EP2: equ 04h ; MASK: enable/disable USB Endpoint 2 interrupt
0002 INT_MSK1_USB_EP1: equ 02h ; MASK: enable/disable USB Endpoint 1 interrupt
0001 INT_MSK1_USB_EP0: equ 01h ; MASK: enable/disable USB Endpoint 0 interrupt
0000
00E2 INT_VC: equ E2h ; Interrupt vector register (RC)
0000
0000 ;------------------------------------------------------
0000 ; System Status and Control Registers
0000 ;------------------------------------------------------
0000 ; Register bank 1.
0000 ;------------------------------------------------------
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register 0 (RW)
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0000
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0000
0000 ;------------------------------------------------------
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
00FF CPU_SCR: equ FFh ; CPU Status and Control Register (#)
0080 CPU_SCR_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR], ~CPU_SCR_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPU_SCR_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPU_SCR_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
00F8 bSSC_KEY1: equ F8h ; supervisory key
00F9 bSSC_KEYSP: equ F9h ; supervisory stack ptr key
00FA bSSC_TABLE_TableId: equ FAh ; table ID
0000
003A OPER_KEY: equ 3Ah ; operation key
0000 ;--------------------------------
0000 ; SSC_Action macro command codes
0000 ;--------------------------------
0001 FLASH_READ: equ 1 ; flash read command
0002 FLASH_WRITE: equ 2 ; flash write command
0003 FLASH_ERASE: equ 3 ; flash erase command
0000
0006 TABLE_READ: equ 6 ; table read command
0007 FLASH_CHECKSUM: equ 7 ; flash checksum calculation command
0008 CALIBRATE0: equ 8 ; Calibrate without checksum
0009 CALIBRATE1: equ 9 ; Calibrate with checksum
0000 ;--------------------------------
0000 ; SSC_Action table read addresses
0000 ;--------------------------------
00F8 SILICON_ID_1: equ F8h ; first byte of silicon ID
00F9 SILICON_ID_0: equ F9h ; second byte of silicon ID
00F8 VOLTAGE_TRIM_3V: equ F8h ; 3.3V internal voltage reference trim value
00F9 OSCILLATOR_TRIM_3V: equ F9h ; 3.3V internal main oscillator trim value
00FC VOLTAGE_TRIM_5V: equ FCh ; 5V internal voltage reference trim value
00FD OSCILLATOR_TRIM_5V: equ FDh ; 5V internal main oscillator trim value
0000 ;-----------------------------------------------------------------------------
0000 ; MACRO NAME: SSC_Action
0000 ;
0000 ; DESCRIPTION:
0000 ; Performs locally defined supervisory operations.
0000 ; Macro Instantiation: SSC_Action bOperation
0000 ;
0000 ; !!! DO NOT CHANGE THIS CODE !!!
0000 ; This sequence of opcodes provides a
0000 ; signature for the debugger and ICE.
0000 ; !!! DO NOT CHANGE THIS CODE !!!
0000 ;
0000 ; ARGUMENTS:
0000 ; BYTE bOperation - specified supervisory operation - defined operations
0000 ; are: FLASH_WRITE, FLASH_ERASE, FLASH_READ, TABLE_READ,
0000 ; FLASH_CHECKSUM, PROTECT_BLOCK
0000 ;
0000 ; RETURNS:
0000 ; none.
0000 ;
0000 ; SIDE EFFECTS:
0000 ; A and X registers are destroyed
0000 ;
0000 ; PROCEDURE:
0000 ; 1) specify a 3 byte stack frame. Save in [KEYSP]
0000 ; 2) insert the flash Supervisory key in [KEY1]
0000 ; 3) store function code in A
0000 ; 4) call the supervisory code
0000 ;-----------------------------------------------------------------------------
0000 macro SSC_Action
0000 mov X, SP ; copy SP into X
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