?? int1.lis
字號:
00FF CPU_SCR: equ FFh ; CPU Status and Control Register (#)
0080 CPU_SCR_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR], ~CPU_SCR_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPU_SCR_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPU_SCR_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0000 SYSTEM_STACK_BASE_ADDR: equ 0h
0000 SYSTEM_LARGE_MEMORY_MODEL: equ 0
0001 SYSTEM_SMALL_MEMORY_MODEL: equ 1
0001 SYSTEM_TOOLS: equ 1
0001 SYSTEM_IDXPG_TRACKS_STK_PP: equ 1
0000 SYSTEM_IDXPG_TRACKS_IDX_PP: equ 0
0000 SYSTEM_MULTIPAGE_STACK: equ 0
0000
0000
0000 ; ******* Function Class Definitions *******
0000 ;
0000 ; These definitions are used to describe RAM access patterns. They provide
0000 ; documentation and they control prologue and epilogue macros that perform
0000 ; the necessary housekeeping functions for large memory model devices like
0000 ; the CY8C27x66 and CY8C29x66.
0000
0001 RAM_USE_CLASS_1: equ 1 ; PUSH, POP & I/O access
0002 RAM_USE_CLASS_2: equ 2 ; Indexed address mode on stack page
0004 RAM_USE_CLASS_3: equ 4 ; Indexed address mode to any page
0008 RAM_USE_CLASS_4: equ 8 ; Direct/Indirect address mode access
0000
0000
0000 ; ******* Page Pointer Manipulation Macros *******
0000 ;
0000 ; Most of the following macros are conditionally compiled so they only
0000 ; produce code if the large memory model is selected.
0000
0000 ;-----------------------------------------------
0000 ; Set Stack Page Macro
0000 ;-----------------------------------------------
0000 ;
0000 ; DESC: Modify STK_PP in the large or small memory Models.
0000 ;
0000 ; INPUT: Constant (e.g., SYSTEM_STACK_PAGE) that specifies the RAM page on
0000 ; which stack operations like PUSH and POP store and retrieve their
0000 ; data
0000 ;
0000 ; COST: 8 instruction cycles (in LMM only)
0000
0000 macro RAM_SETPAGE_STK( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[STK_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_CUR( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[CUR_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_IDX( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[IDX_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_MVR( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[MVR_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_MVW( PG_NUMBER )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 mov reg[MVW_PP], @PG_NUMBER
0000 ENDIF
0000 macro RAM_SETPAGE_IDX2STK
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_MULTIPAGE_STACK )
0000 mov A, reg[STK_PP]
0000 mov reg[IDX_PP], A
0000 ELSE
0000 RAM_SETPAGE_IDX SYSTEM_STACK_PAGE
0000 ENDIF
0000 ENDIF
0000 macro RAM_CHANGE_PAGE_MODE( MODE )
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
0000 or F, FLAG_PGMODE_MASK & @MODE
0000 ENDIF
0000 macro RAM_SET_NATIVE_PAGING
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
0000 ENDIF ; PGMODE LOCKED
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 or F, FLAG_PGMODE_10b ; LMM with independent IndexPage
0000 ENDIF ; PGMODE FREE
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_RESTORE_NATIVE_PAGING
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 RAM_CHANGE_PAGE_MODE FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
0000 ENDIF ; PGMODE LOCKED
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 RAM_CHANGE_PAGE_MODE FLAG_PGMODE_10b ; LMM with independent IndexPage
0000 ENDIF ; PGMODE FREE
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_X_POINTS_TO_STACKPAGE
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 or F, FLAG_PGMODE_01b
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_X_POINTS_TO_INDEXPAGE
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 and F, ~FLAG_PGMODE_01b
0000 ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
0000 macro RAM_PROLOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
0000 RAM_X_POINTS_TO_STACKPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
0000 RAM_X_POINTS_TO_INDEXPAGE ; exit native paging mode!
0000 ENDIF
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro RAM_EPILOGUE( ACTUAL_CLASS )
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_1 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_1
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_2 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_2
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_3 )
0000 RAM_RESTORE_NATIVE_PAGING
0000 ENDIF ; RAM_USE_CLASS_3
0000
0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE PRV_PP
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
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