?? usb.c.svn-base
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
#include <windows.h>
#include <halether.h>
#include <bsp.h>
#include "loader.h"
#define DMABUFFER 0x32000000
#define USBDEV_BASE 0xB0B00000 // VIRTUAL Address
#define pISR (*(volatile unsigned *)(0x30000000+0x18)) // Virtual Address 0x0 is mapped to 0x30000000, ISR Address is VA 0x18
extern void delayLoop(int count);
#define Outp32(addr, data) (*(volatile UINT32 *)(addr) = (data))
#define Outp16(addr, data) (*(volatile UINT16 *)(addr) = (data))
#define Outp8(addr, data) (*(volatile UINT8 *)(addr) = (data))
#define Inp32(addr, data) (data = (*(volatile UINT32 *)(addr)))
#define Inp16(addr, data) (data = (*(volatile UINT16 *)(addr)))
#define Inp8(addr, data) (data = (*(volatile UINT16 *)(addr)))
#define Input32(addr) (*(volatile UINT32 *)(addr))
typedef enum
{
INDEX_REG = (USBDEV_BASE+0x00), // Index register
EP_INT_REG = (USBDEV_BASE+0x04), // EP Interrupt pending and clear
EP_INT_EN_REG = (USBDEV_BASE+0x08), // EP Interrupt enable
FUNC_ADDR_REG = (USBDEV_BASE+0x0c), // Function address
FRAME_NUM_REG = (USBDEV_BASE+0x10), // Frame number
EP_DIR_REG = (USBDEV_BASE+0x14), // Endpoint direction
TEST_REG = (USBDEV_BASE+0x18), // Test register
SYS_STATUS_REG = (USBDEV_BASE+0x1c), // System status
SYS_CON_REG = (USBDEV_BASE+0x20), // System control
EP0_STATUS_REG = (USBDEV_BASE+0x24), // Endpoint 0 status
EP0_CON_REG = (USBDEV_BASE+0x28), // Endpoint 0 control
EP_STATUS_REG = (USBDEV_BASE+0x2c), // Endpoints status
EP_CON_REG = (USBDEV_BASE+0x30), // Endpoints control
BYTE_READ_CNT_REG = (USBDEV_BASE+0x34), // read count
BYTE_WRITE_CNT_REG = (USBDEV_BASE+0x38), // write count
MAX_PKT_REG = (USBDEV_BASE+0x3c), // Max packet size
DMA_CON_REG = (USBDEV_BASE+0x40), // DMA control
DMA_CNT_REG = (USBDEV_BASE+0x44), // DMA count
DMA_FIFO_CNT_REG = (USBDEV_BASE+0x48), // DMA FIFO count
DMA_TOTAL_CNT1_REG = (USBDEV_BASE+0x4c), // DMA Total count1
DMA_TOTAL_CNT2_REG = (USBDEV_BASE+0x50), // DMA Total count2
DMA_IF_CON_REG = (USBDEV_BASE+0x84), // DMA interface Control
DMA_MEM_BASE_ADDR = (USBDEV_BASE+0x88), // Mem Base Addr
DMA_MEM_CURRENT_ADDR = (USBDEV_BASE+0x8c), // Mem current Addr
EP0_FIFO = (USBDEV_BASE+0x60), // Endpoint 0 FIFO
EP1_FIFO = (USBDEV_BASE+0x64), // Endpoint 1 FIFO
EP2_FIFO = (USBDEV_BASE+0x68), // Endpoint 2 FIFO
EP3_FIFO = (USBDEV_BASE+0x6c), // Endpoint 3 FIFO
EP4_FIFO = (USBDEV_BASE+0x70), // Endpoint 4 FIFO
FCON = (USBDEV_BASE+0x100) // Burst Fifo Control
} USBD20_REGS ;
// Descriptor Types
typedef enum
{
DEVICE_TYPE_ = 0x1,
CONFIGURATION_TYPE,
STRING_TYPE,
INTERFACE_TYPE_,
ENDPOINT_TYPE
} DESC_TYPE;
// configuration descriptor: bmAttributes
typedef enum
{
CONF_ATTR_DEFAULT = 0x80, // Spec 1.0 it was BUSPOWERED bit.
CONF_ATTR_REMOTE_WAKEUP = 0x20,
CONF_ATTR_SELFPOWERED = 0x40
} DESC_CONF;
// endpoint descriptor
typedef enum
{
EP_ADDR_IN = 0x80,
EP_ADDR_OUT = 0x00,
EP_ATTR_CONTROL = 0x0,
EP_ATTR_ISOCHRONOUS = 0x1,
EP_ATTR_BULK = 0x2,
EP_ATTR_INTERRUPT = 0x3
} DESC_ENDPT;
typedef enum
{
EP0, EP1, EP2, EP3, EP4
} EP_INDEX;
typedef enum
{
USB_FULL, USB_HIGH
} USB_SPEED;
typedef enum
{
USB_CPU, USB_DMA
} USB_OP;
typedef struct USB_DEVICE_DESCRIPTOR
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bcdUSBL;
UINT8 bcdUSBH;
UINT8 bDeviceClass;
UINT8 bDeviceSubClass;
UINT8 bDeviceProtocol;
UINT8 bMaxPacketSize0;
UINT8 idVendorL;
UINT8 idVendorH;
UINT8 idProductL;
UINT8 idProductH;
UINT8 bcdDeviceL;
UINT8 bcdDeviceH;
UINT8 iManufacturer;
UINT8 iProduct;
UINT8 iSerialNumber;
UINT8 bNumConfigurations;
} USB_DEVICE_DESCRIPTOR;
typedef struct DEVICE_REQUEST
{
UINT8 bmRequestType;
UINT8 bRequest;
UINT8 wValue_L;
UINT8 wValue_H;
UINT8 wIndex_L;
UINT8 wIndex_H;
UINT8 wLength_L;
UINT8 wLength_H;
} DEVICE_REQUEST;
typedef struct USB_CONFIGURATION_DESCRIPTOR
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 wTotalLengthL;
UINT8 wTotalLengthH;
UINT8 bNumInterfaces;
UINT8 bConfigurationValue;
UINT8 iConfiguration;
UINT8 bmAttributes;
UINT8 maxPower;
} USB_CONFIGURATION_DESCRIPTOR;
typedef struct USB_INTERFACE_DESCRIPTOR
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bInterfaceNumber;
UINT8 bAlternateSetting;
UINT8 bNumEndpoints;
UINT8 bInterfaceClass;
UINT8 bInterfaceSubClass;
UINT8 bInterfaceProtocol;
UINT8 iInterface;
} USB_INTERFACE_DESCRIPTOR;
typedef struct USB_ENDPOINT_DESCRIPTOR
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bEndpointAddress;
UINT8 bmAttributes;
UINT8 wMaxPacketSizeL;
UINT8 wMaxPacketSizeH;
UINT8 bInterval;
} USB_ENDPOINT_DESCRIPTOR;
// EP0 CSR register Bits
#define EP0_SENT_STALL (0x01<<4)
#define EP0_DATA_END (0x01<<3)
#define EP0_SETUP_END (0x03<<2)
#define EP0_TX_SUCCESS (0x01<<1)
#define EP0_RX_SUCCESS (0x01<<0)
// Defines for Endpoint CSR Register Bits
#define DMA_TOTAL_COUNT_ZERO (0x1<<9)
#define EP_FIFO_FLUSH (0x1<<6)
#define EP_SENT_STALL (0x1<<5)
#define EP_TX_SUCCESS (0x1<<1)
#define EP_RX_SUCCESS (0x1<<0)
#define EP0_STATE_INIT (0)
#define EP0_STATE_GD_DEV_0 (11)
#define EP0_STATE_GD_DEV_1 (12)
#define EP0_STATE_GD_DEV_2 (13)
#define EP0_STATE_GD_CFG_0 (21)
#define EP0_STATE_GD_CFG_1 (22)
#define EP0_STATE_GD_CFG_2 (23)
#define EP0_STATE_GD_CFG_3 (24)
#define EP0_STATE_GD_CFG_4 (25)
#define EP0_STATE_GD_CFG_ONLY_0 (41)
#define EP0_STATE_GD_CFG_ONLY_1 (42)
#define EP0_STATE_GD_IF_ONLY_0 (44)
#define EP0_STATE_GD_IF_ONLY_1 (45)
#define EP0_STATE_GD_EP0_ONLY_0 (46)
#define EP0_STATE_GD_EP1_ONLY_0 (47)
#define EP0_STATE_GD_EP2_ONLY_0 (48)
#define EP0_STATE_GD_EP3_ONLY_0 (49)
#define EP0_STATE_GD_STR_I0 (30)
#define EP0_STATE_GD_STR_I1 (31)
#define EP0_STATE_GD_STR_I2 (32)
#define EP0_STATE_GD_DEV_QUALIFIER (33)
#define EP0_INTERFACE_GET (34)
#define EP0_GET_STATUS0 (35)
#define EP0_GET_STATUS1 (36)
#define EP0_GET_STATUS2 (37)
#define EP0_GET_STATUS3 (38)
#define EP0_GET_STATUS4 (39)
// SPEC1.1
// Standard bmRequestType (Type)
#define STANDARD_TYPE 0x00
#define CLASS_TYPE 0x20
#define VENDOR_TYPE 0x40
#define RESERVED_TYPE 0x60
// Standard bmRequestType (Recipient)
// #define DEVICE_bmREQUEST_RECIPIENT(oDeviceRequest) ((m_poDeviceRequest->bmRequestType) & 0x07)
#define DEVICE_RECIPIENT 0
#define INTERFACE_RECIPIENT 1
#define ENDPOINT_RECIPIENT 2
#define OTHER_RECIPIENT 3
// Standard bRequest codes
#define STANDARD_GET_STATUS 0
#define STANDARD_CLEAR_FEATURE 1
#define STANDARD_RESERVED_1 2
#define STANDARD_SET_FEATURE 3
#define STANDARD_RESERVED_2 4
#define STANDARD_SET_ADDRESS 5
#define STANDARD_GET_DESCRIPTOR 6
#define STANDARD_SET_DESCRIPTOR 7
#define STANDARD_GET_CONFIGURATION 8
#define STANDARD_SET_CONFIGURATION 9
#define STANDARD_GET_INTERFACE 10
#define STANDARD_SET_INTERFACE 11
#define STANDARD_SYNCH_FRAME 12
// Descriptor types
#define DEVICE_DESCRIPTOR 1
#define CONFIGURATION_DESCRIPTOR 2
#define STRING_DESCRIPTOR 3
#define INTERFACE_DESCRIPTOR 4
#define ENDPOINT_DESCRIPTOR 5
#define DEVICE_QUALIFIER 6
#define OTHER_SPEED_CONFIGURATION 7
// string descriptor
#define LANGID_US_L (0x09)
#define LANGID_US_H (0x04)
// USB Endpoints states
#define EP0_STATE_IDLE (0)
#define EP0_STATE_TRANSFER (1)
#define EP0_STATE_RECEIVER (2)
#define BULK_OUT_STATUS_NOSTALL (0x0000)
#define BULK_OUT_STATUS_STALL (0x0001)
#define DEVICE_STATUS_DEFAULT (0x0000)
#define DEVICE_STATUS_SELFPOWERED (0x0001)
#define DEVICE_STATUS_REMOTEWAKEUP (0x0002)
#define DEVICE_DESC_SIZE 18
#define STRING_DESC0_SIZE 4
#define STRING_DESC1_SIZE 22
#define STRING_DESC2_SIZE 44
#define CONFIG_DESC_TOTAL_SIZE 32
#define CONFIG_DESC_SIZE 9
#define INTERFACE_DESC_SIZE 9
#define ENDPOINT_DESC_SIZE 7
#define DEVICE_QUALIFIER_SIZE 10
#define OTHER_SPEED_CONFIGURATION_SIZE 9
// INT_REG status value
#define INT_ERR (0xff80)
#define INT_REG_ERROR (0xff1<<6)
#define INT_REG_VBUS (0x1<<8)
#define INT_REG_VBUS_CLEAR (0x1<<6)
#define INT_REG_HSP (0x1<<4)
#define INT_REG_SDE (0x1<<3)
#define INT_REG_RESET (0x1)
#define INT_REG_RESUME (0x1<<2)
#define INT_REG_SUSPEND (0x1<<1)
#define INT_REG_EP4 (0x1<<4)
#define INT_REG_EP3 (0x1<<3)
#define INT_REG_EP2 (0x1<<2)
#define INT_REG_EP1 (0x1<<1)
#define INT_REG_EP0 (0x1)
#define INT_DTB_MISMATCH (0x1FF<<7)
// USB Dma Operation
#define DMA_AUTO_RX_DISABLE (0x1<<5)
#define DMA_FLY_ENABLE (0x1<<4)
#define DMA_FLY_DISABLE (0x0<<4)
#define DMA_DEMEND_ENABLE (0x1<<3)
#define DMA_DEMEND_DISABLE (0x0<<3)
#define DMA_TX_START (0x1<<2)
#define DMA_TX_STOP (0x0<<2)
#define DMA_RX_START (0x1<<1)
#define DMA_RX_STOP (0x0<<1)
#define USB_DMA_MODE (0x1<<0)
#define USB_INT_MODE (0x0<<0)
#define MAX_BURST_INCR16 (0x3<<0)
#define MAX_BURST_INCR8 (0x2<<0)
#define MAX_BURST_INCR4 (0x1<<0)
#define DMA_ENABLE (0x1<<8)
#define DMA_DISABLE (0x0<<8)
const UINT8 aDeviceQualifierDescriptor[] =
{
0x0a, // 0 desc size
0x06, // 1 desc type (DEVICE)
0x00, // 2 USB release
0x02, // 3 => 2.00
0x00, // 4 class
0x00, // 5 subclass
0x00, // 6 protocol
64, // 7 max pack size
0x01, // 8 number of other-speed configuration
0x00, // 9 reserved
};
const UINT8 aDescStr0[]=
{
4, STRING_DESCRIPTOR, LANGID_US_L, LANGID_US_H, // codes representing languages
};
const UINT8 aDescStr1[]= // Manufacturer
{
(0x14+2), STRING_TYPE,
'S', 0x0, 'y', 0x0, 's', 0x0, 't', 0x0, 'e', 0x0, 'm', 0x0, ' ', 0x0, 'M', 0x0,
'C', 0x0, 'U', 0x0,
};
const UINT8 aDescStr2[]= // Product
{
(0x2a+2), STRING_TYPE,
'S', 0x0, 'E', 0x0, 'C', 0x0, ' ', 0x0, 'S', 0x0, '3', 0x0, 'C', 0x0, '2', 0x0,
'4', 0x0, '4', 0x0, '3', 0x0, 'X', 0x0, ' ', 0x0, 'T', 0x0, 'e', 0x0, 's', 0x0,
't', 0x0, ' ', 0x0, 'B', 0x0, '/', 0x0, 'D', 0x0
};
UINT32 g_uEp0MaxPktSize;
UINT32 g_uEp1MaxPktSize;
UINT32 g_uEp3MaxPktSize;
UINT32 g_uEp0State;
USB_SPEED g_eSpeed;
USB_DEVICE_DESCRIPTOR g_oDescDevice;
DEVICE_REQUEST g_oDeviceRequest;
UINT32 g_uBulkInAddr;
UINT32 g_uBulkInCount;
UINT32 g_uDownloadFileSize;
UINT32 g_uDownloadAddress = DMABUFFER;
volatile UINT32 readPtIndex;
volatile UINT8 *g_pDownPt;
UINT32 g_uEp0SubState;
#define g_eOpMode USB_CPU
typedef struct USB_GET_STATUS
{
UINT8 Device;
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