//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
#ifndef __NAND_H__
#define __NAND_H__

#define MAGNETO 0

//#define NAND_BLOCK_CNT		(1024 * 4)	  /* Each Plane has 1024 Blocks   */
#define NAND_PAGE_CNT		(256)			/* Each Block has 32 Pages	  */
#define NAND_PAGE_SIZE		(512)		   /* Each Page has 512 Bytes	  */
#define NAND_BLOCK_SIZE	(NAND_PAGE_CNT * NAND_PAGE_SIZE)

#define USE_NFCE				0
#define USE_GPIO				0
#define SPARE_SIZE				16

#define BADBLOCKMARK                0x00

#define CMD_READID			0x90		//  ReadID
#define CMD_READ			0x00		//  Read
#define CMD_READ2			0x50		//  Read2
#define CMD_READ3               0x30        //  Read3
#define CMD_RESET			0xff		//  Reset
#define CMD_ERASE			0x60		//  Erase phase 1
#define CMD_ERASE2			0xd0		//  Erase phase 2
#define CMD_WRITE			0x80		//  Write phase 1
#define CMD_WRITE2			0x10		//  Write phase 2
#define CMD_STATUS			0x70		//  STATUS
#define CMD_RDI                 0x85        //  Random Data Input
#define CMD_RDO                 0x05        //  Random Data Output
#define CMD_RDO2                0xE0        //  Random Data Output

//  Status bit pattern
#define STATUS_READY		0x40		//  Ready
#define STATUS_ERROR		0x01		//  Error

#define LB_BLOCK_LOOP			1
#define SB_BLOCK_LOOP			8


/* !!! Maximum Delay Setting, Please Adjust these value to Optimize */
// 266Mhz: 1,6,1.
#define TACLS			7//1	 // 1
#define TWRPH0			7//4//6 
#define TWRPH1			7//1//2 	// 2 

#define NF_CMD(cmd)			{s2443NAND->NFCMD   =  (unsigned char)(cmd);}
#define NF_ADDR(addr)		{s2443NAND->NFADDR  =  (unsigned char)(addr);}	



#define NF_nFCE_L()				{s2443NAND->NFCONT &= ~(1<<1);}
#define NF_nFCE_H()				{s2443NAND->NFCONT |=  (1<<1);}
#define NF_RDESTST				(s2443NAND->NFECCERR1)

//-----------------------------------------

#define NF_RSTECC()				{s2443NAND->NFCONT |=  ((1<<5) | (1<<4));}

#define NF_MECC_UnLock()		{s2443NAND->NFCONT &= ~(1<<7);}
#define NF_MECC_Lock()			{s2443NAND->NFCONT |= (1<<7);}
#define NF_SECC_UnLock()		{s2443NAND->NFCONT &= ~(1<<6);}
#define NF_SECC_Lock()			{s2443NAND->NFCONT |= (1<<6);}

#define NF_CLEAR_RB()			{s2443NAND->NFSTAT |=  (1<<4);}	// Have write '1' to clear this bit.

#define NF_DETECT_RB()			{ while((s2443NAND->NFSTAT&0x11)!=0x11);} // RnB_Transdetect & RnB
#define NF_WAITRB()		 		{while (!(s2443NAND->NFSTAT & (1<<0))) ; } 


#define NF_RDDATA_BYTE() 				(s2443NAND->NFDATA)
#define NF_RDDATA_WORD() 				(*(UINT32 *)0xb1400010)

#define NF_WRDATA_BYTE(data)			 {s2443NAND->NFDATA  =  (UINT8)(data);}
#define NF_WRDATA_WORD(data)			 {*(UINT32 *)0xb1400010  =  (UINT32)(data);}

#define NF_RDMECC0()			(s2443NAND->NFMECC0)
#define NF_RDMECC1()			(s2443NAND->NFMECC1)
#define NF_RDSECC()				(s2443NAND->NFSECC)

#define NF_RDMECCD0()			(s2443NAND->NFMECCD0)
#define NF_RDMECCD1()			(s2443NAND->NFMECCD1)
#define NF_RDSECCD()			(s2443NAND->NFSECCD)

#define NF_WRMECCD0(data)		{s2443NAND->NFMECCD0 = (data);}
#define NF_WRMECCD1(data)		{s2443NAND->NFMECCD1 = (data);}
#define NF_WRSECCD(data)		{s2443NAND->NFSECCD = (data);}


#define NF_RDSTAT				(s2443NAND->NFSTAT)

#endif	// __NAND_H_.