?? s3c2443.inc.svn-base
字號:
GBLA CHANGE_CLK_EBOOT
GBLA CHANGE_CLK_OAL
CHANGE_CLK_EBOOT SETA 1 ; 1:RE-Setting PLL value(refer startup.s in Eboot)
CHANGE_CLK_OAL SETA 1 ; 1:RE-Setting PLL value(refer startup.s in oal)
; ========================================================================
; PLL Value setting
; EBOOT and Kernel refers this value.
;=====================================================================================
; Fin = 12MHz,
;
; MPLLout = (2m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV, s=SDIV, Fin=10~30MHz
; (17,1,1)=300Mhz, (92,3,1)=400Mhz, (67,2,1)=450Mhz, (81,2,1)=534Mhz,
; (17,1,0)=600Mhz, (92,3,0)=800Mhz
;
; EPLLout = (m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV+2, s=SDIV, Fin=10~100MHz
; (28,1,2)=36Mhz, (40,1,2)=48Mhz, (22,1,1)=60Mhz, (28,1,1)=72Mhz, (34,1,1)=84Mhz
; (40,1,1)=96Mhz
;=====================================================================================
GBLA CLKVAL
GBLA DVSON
GBLA HCLKVAL
CLKVAL SETA 533
[ CLKVAL = 300
DVSON SETA 0
HCLKVAL SETA 100
Startup_MPLL EQU 300000000
Startup_Mdiv EQU 17
Startup_Pdiv EQU 1
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x2 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 400
DVSON SETA 0
HCLKVAL SETA 100
Startup_MPLL EQU 400000000
Startup_Mdiv EQU 92
Startup_Pdiv EQU 3
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x3 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 400133
DVSON SETA 0
HCLKVAL SETA 133
Startup_MPLL EQU 400000000
Startup_Mdiv EQU 92
Startup_Pdiv EQU 3
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x2 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x2 : HCLK = PREDIV_CLK/3
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 533
DVSON SETA 0
HCLKVAL SETA 133
Startup_MPLL EQU 533000000
Startup_Mdiv EQU 81
Startup_Pdiv EQU 2
Startup_Sdiv EQU 1
Startup_ARMCLKdiv EQU 0 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x1 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 500
DVSON SETA 0
HCLKVAL SETA 120
Startup_MPLL EQU 500000000
Startup_Mdiv EQU 34
Startup_Pdiv EQU 1
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x3 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
Startup_EMdiv EQU 40 ; 96Mhz
Startup_EPdiv EQU 1
Startup_ESdiv EQU 1
; EBICON(0x4E80_0008) setting
;[31:11] Reserved
;[10] BANK3 0:SROM, 1:CF
;[9] BANK2 0:SROM, 1:CF
;[8] BANK1 0:SROM, 1:NAND
GBLA EBICON_VAL
;EBICON_VAL SETA ((1<<7)+(1<<6)+(1<<5)+(0<<4)+(0<<3)+(1<<2)+(0<<1)+(0<<0)) ; BANK[7:2]=SDRAM/SDRAM/RAM/CF/NAND/SRAM
EBICON_VAL SETA ((0<<10)+(0<<9)+(1<<8)+(1<<2)+(0<<1)+(0<<0)) ; BANK[7:2]=SDRAM/SDRAM/RAM/CF/NAND/SRAM
;======================================================================================
; MEM config [SDR, DDR]
;======================================================================================
GBLL mDDR ; 256Mbit x16 x2ea = 512Mbit mem size
; GBLL mSDR ; 256Mbit x16 x2ea = 512Mbit mem size
IF :DEF: mSDR
;---------------------------------------
; BANKCFG register : DRAM configure
;---------------------------------------
RASBW0 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
RASBW1 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
CASBW0 EQU 1 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
CASBW1 EQU 1 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
ADDRCFG0 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
ADDRCFG1 EQU 0 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
MEMCFG EQU 1 ; Ext.Mem 00=SDR,01=MSDR,10=DDR, 11=MDDR
BW EQU 0 ; Bus width 00=32bit,01=16bit
;---------------------------------------
; BANKCON1 register : DRAM timing control
;---------------------------------------
DQS EQU 0 ; [30:28] 000b is the best.
Reserved0 EQU 1 ; [27:26] 01b (should be set)
BStop EQU 0 ; read burst stop control
WBUF EQU 1 ; write buffer control
AP EQU 1 ; auto precharge control
PWRDN EQU 0 ; power down mode
BANKINIT EQU 0 ;3 ; DRAM initialize control
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
;tRAS EQU 5 ; Row active time
;tRC EQU 7 ; Row cycle time
;CL EQU 3 ; CAS latency control
;tRCD EQU 2 ; RAS to CAS delay
;tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; BANKCON3 register : MRS/EMRS register
;---------------------------------------
BA_EMRS EQU 2 ; BA : EMRS
DS EQU 0 ;2 ; Driver strength
PASR EQU 0 ; PASR
BA_MRS EQU 0 ; BA : MRS
TM EQU 0 ; Test Mode - mode register set
CL_MRS EQU 3 ; CAS Latency
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
;REFCYC EQU 787 ; refresh cycle
; 100MHz=787, 133MHz=1053
ELSE
;---------------------------------------
; BANKCFG register : DRAM configure
;---------------------------------------
RASBW0 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
RASBW1 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
CASBW0 EQU 2 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
CASBW1 EQU 2 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
ADDRCFG0 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
ADDRCFG1 EQU 0 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
MEMCFG EQU 3 ; Ext.Mem 00=SDR,01=MSDR,10=DDR, 11=MDDR
BW EQU 1 ; Bus width 00=32bit,01=16bit
;---------------------------------------
; BANKCON1 register : DRAM timing control
;---------------------------------------
DQS EQU 0 ;4 ; [30:28] 000b is the best.
Reserved0 EQU 1 ; [27:26] 01b (should be set)
BStop EQU 0 ; read burst stop control
WBUF EQU 1 ; write buffer control
AP EQU 1 ; auto precharge control
PWRDN EQU 0 ; power down mode
BANKINIT EQU 0 ; 3 ; DRAM initialize control
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
;tRAS EQU 5 ; Row active time
;tRC EQU 7 ; Row cycle time
;CL EQU 3 ; CAS latency control
;tRCD EQU 2 ; RAS to CAS delay
;tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; BANKCON3 register : MRS/EMRS register
;---------------------------------------
BA_EMRS EQU 2 ; BA : EMRS
DS EQU 0 ;3 ; Driver strength
PASR EQU 0 ; PASR
BA_MRS EQU 0 ; BA : MRS
TM EQU 0 ; Test Mode - mode register set
CL_MRS EQU 3 ; CAS Latency
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
;REFCYC EQU 787 ; refresh cycle
; 100MHz=787, 133MHz=1053
;---------------------------------------------------------------------------
ENDIF
[ HCLKVAL = 133
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
tRAS EQU 6 ; Row active time
tRC EQU 9 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
REFCYC EQU 1037 ; refresh cycle
|
[ HCLKVAL = 120
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
tRAS EQU 5 ; Row active time
tRC EQU 8 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
REFCYC EQU 936 ; refresh cycle
|
[ HCLKVAL = 110
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
tRAS EQU 5 ; Row active time
tRC EQU 7 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
REFCYC EQU 858 ; refresh cycle
|
[ HCLKVAL = 100
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
tRAS EQU 4 ; Row active time
tRC EQU 7 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
REFCYC EQU 780 ; refresh cycle
|
;---------------------------------------
; BANKCON2 register : DRAM timing control
;---------------------------------------
tRAS EQU 4 ; Row active time
tRC EQU 7 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
REFCYC EQU 514 ; refresh cycle
]
]
]
]
END
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -