/*!
 *
 * \file    mxd_sdk_api.h
 *
 * \brief    SDK API header file.
 *
 * Header file of the functions declaration about DTMB SDK
 *
 * \par    Include files
 * - mxd_sdk_data.h
 *
 * \par    Copyright (c) 2007 Maxscend Technologies Inc. All rights reserved
 *
 * PROPRIETARY RIGHTS of Maxscend Technologies Inc. are involved in
 * the subject matter of this material.  All manufacturing, reproduction, 
 * use, and sales rights pertaining to this subject matter are governed 
 * by the license agreement.  The recipient of this software implicitly 
 * accepts the terms of the license.
 *
 * \version
 * Revision of last commit: $Rev:: 351                                      $
 * Author of last commit  : $Author:: MAXSCEND\yang.liu                     $
 * Date of last commit    : $Date:: 2007-12-11 20:00:28 +0800               $
 *
 */
 
#ifndef __MXD_SDK_API_H__
#define __MXD_SDK_API_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "mxd_sdk_data.h"

/**********************************************************************************
 * 
 * Section Function Declarations & Const Definitions
 *
 **********************************************************************************
 */

/*
 * MDW Section
 */
#define DTMB_LOCK_STATUS_SEM_BIT 0
#define DTMB_LOCK_STATUS 1
#define DTMB_UNLOCK_STATUS 0

#define DEV_MODE_SET_BY_HARDWARE 0x00
#define MODE_SEL_PIN_SET_MODE_BIT 0x01
#define MODE_SEL_REG_SET_MODE_BIT 0x00
#define DEV_MODE_DTMB_VAL 0x00

HMXDDEV MXD_API MDW_OpenDevice(IN CONST PIL_DEVICECONFIG pPIL_DeviceConfig, IN CONST PCALLBACK_SETTING_S psCbSetting);
MXD_RTN_CODE_E MXD_API MDW_CloseDevice(IN HMXDDEV hDevice);
MXD_U32 MXD_API MDW_GetSystemSnr(IN HMXDDEV hDevice);
MXD_U32 MXD_API MDW_GetSystemRssi(IN HMXDDEV hDevice);
MXD_U32 MXD_API MDW_GetSystemPer(IN HMXDDEV hDevice, IN SYSTEM_PER_TYPE_E ePerType);
MXD_RTN_CODE_E MXD_API MDW_ChannelSearch(IN HMXDDEV hDevice, IN MXD_U32 freqHz, IN MXD_U32 milliseconds, OUT VOID *psChannelInfo);
MXD_RTN_CODE_E MXD_API MDW_GetLockStatus(IN HMXDDEV hDevice);

MXD_RTN_CODE_E MXD_API MDW_SetDeviceMode(IN HMXDDEV hDevice, IN DEVICE_WORK_MODE_E eDeviceMode);
MXD_RTN_CODE_E MXD_API MDW_SetupInterface (IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API MDW_CloseInterface (IN HMXDDEV hDevice);

/*
 * Tuner Section
 */
#ifndef __TUNER_EXT_CTRL__
#define TUNER_CHK_MAX_NUM 20
#define TUNER_RW_ACCESS_FINISH 0x01

MXD_RTN_CODE_E MXD_API MDW_TuneFreq(IN HMXDDEV hDevice, IN MXD_U32 freqHz);
MXD_RTN_CODE_E MXD_API TIF_ReadTunerReg(IN HMXDDEV hDevice, IN MXD_U8 regAddr, OUT MXD_U8 *pRegVal);
MXD_RTN_CODE_E MXD_API TIF_WriteTunerReg(IN HMXDDEV hDevice, IN MXD_U8 regAddr, IN MXD_U8 regVal);
#endif /* end of #ifndef __TUNER_EXT_CTRL__ */

/*
 * Device Configuration Section
 */
VOID MXD_API MXD_Porting_DeviceConfig( IN PDEMOD_PROPERTY_S pDemodProperty, IN PTUNER_PROPERTY_S pTunerProperty);

/*
 * Callback Sectin
 */
extern CALLBACK_SETTING_S gsCallbackSetting;

/**********************************************************************************
 * 
 * Section Function Declarations & Const Definitions
 *
 **********************************************************************************
 */

/*
 * DTMB Section
 */
#define __AUTO_DETECT_ALL_MODE__
#define SDI_BYPASS_EN 0
#define CLOCK_GATING_EN 1

#ifndef __EEPROM_USED__
#define MTX_HUFMAN_TABLE_LEN 29184
#else
#define MTX_HUFMAN_TABLE_LEN 2
#endif
extern MXD_U8 mtxHufmanTable[MTX_HUFMAN_TABLE_LEN];


#define UFO_TIMEOUT_THLD 200
#define UFO_MAX_LIMIT 400
#define UFO_OK_THRESHOLD 5
#define CYP_TIMEOUT_THLD 200
#define CPE_SLEEP_TIME 400

#define TPS_ERR_THRESHOLD 5

#define MTXHUFMANTABLE_ADDR mtxHufmanTable
#define MTXTABLE_IN_SDRAM 0x1F00

#define MXD_BIT0 0x0
#define MXD_BIT1 0x1
#define MXD_BIT2 0x2
#define MXD_BIT3 0x3
#define MXD_BIT4 0x4
#define MXD_BIT5 0x5
#define MXD_BIT6 0x6
#define MXD_BIT7 0x7

#define TDP_IF_TYPE_BIT 1
#define TDP_IF_TYPE_ZIF 0

#define DTMB_DATA_BUFFER_FLUSH_BIT MXD_BIT0
#define DTMB_TDP_INT_OFO_RDY_OFFSET 0x0
#define DTMB_TDP_NO_SIGNAL_INT_BIT (0x01<<7)
#define	DTMB_TDP_NO_SIGNAL_INT_SET MXD_BIT7
#define DTMB_TDP_CPE_TIMEOUT_INT_SET (0x01<<6)
#define DTMB_TDP_TPS_FAIL_INT_BIT (0x01<<5)
#define DTMB_TDP_FWT_FAIL_INT_BIT (0x01 << 4)
#define DTMB_TDP_TPS_FAIL_INT_SET MXD_BIT5
#define DTMB_TDP_FTT_FAIL_INT_SET (0x01<<4)
#define DTMB_TDP_FID_FAIL_INT_SET (0x01<<3)
#define DTMB_TDP_TPS_OK_INT_BIT (0x01<<2)
#define DTMB_TDP_TPS_OK_INT_SET MXD_BIT2
#define DTMB_TDP_INIT_OK_INT_BIT MXD_BIT1
#define DTMB_HIC_IR_DATA_FEC_SET  (0x01<<3)
#define DTMB_HIC_IR_DATA_OVERFLOW_SET (0x01<<2)
#define DTMB_HIC_IR_DATA_UNDERFLOW_SET 0x01
#define DTMB_DATA_RDY_INT_SET (0x01 << 1)

#define DTMB_TDP_OFO_VALUE_MINUS_SET (0x1<<5)
#define DTMB_TDP_INIT_FO_VALUE_MINUS_SET (0x1<<7)
#define DTMB_TDP_ZSP_VALUE_MINUS_SET (0x1<<1)
#define DTMB_TDP_FPP_VALUE_MINUS_SET (0x1<<1)
#define TDP_TPS_SUM_I_MINUS_SET (0x1<<7)
#define TDP_TPS_SUM_Q_MINUS_SET (0x1<<7)

#define IF_VAL 8192
#define IF_OUTPUT_VAL 7560
#define INPUT_IF_4_X 32768
#define INPUT_IF_6_X 49152
#define INPUT_IF_12_X 98304

#define DTMB_SDI_SDRM_START_ADDR_VAL 0x0000
#define DTMB_HIC_SDRM_ROW_BADDR_VAL 0x1700
#define DTMB_HIC_SDRM_ROW_EADDR_VAL	0x1eff

#define I2C_BLOCK_BUF_ADDR 0xe4
#define I2C_MTX_BURST_WRITE_ADDR 0xe5

#define PN_420_FIX 0x0
#define PN_420_ROTATE 0x1
#define PN_945_FIX 0x2
#define PN_945_ROTATE 0x3
#define PN_595 0x4

#define IF_2_X_ZIF 0x0
#define IF_4_X_ZIF 0x1
#define IF_3_X_LIF 0x2
#define IF_4_X_LIF 0x3
#define IF_6_X_LIF 0x4
#define IF_12_X_LIF 0x5

#define FRAME_LEN_420 4200
#define FRAME_LEN_945 4725
#define FRAME_LEN_595 4375

#define INTERLEAVE_TYPE_240 0
#define INTERLEAVE_TYPE_720 1

#define QAM_TYPE_4 0
#define QAM_TYPE_16 1
#define QAM_TYPE_64 2
#define QAM_TYPE_32 3
#define QAM_TYPE_4NR 4
#define LDPC_CODE_RATE_0_4 0
#define LDPC_CODE_RATE_0_6 1
#define LDPC_CODE_RATE_0_8 2

#define MISC_RSSI_READ_FREEZE_SET 0x1
#define MISC_BER_READ_FREEZE_SET (0x1<<1)
#define MISC_BLER_READ_FREEZE_SET (0x1<<2)
#define MISC_SNR_READ_FREEZE_SET (0x1<<3)
#define MISC_TPS_READ_FREEZE_SET (0x1<<4)
#define MISC_FPP_READ_FREEZE_SET (0x1<<5)

MXD_RTN_CODE_E MXD_API DTMB_ResetDevice(IN HMXDDEV hDevice);
DEVICE_WORK_MODE_E MXD_API DTMB_DetectMode(IN HMXDDEV hDevice, IN MXD_U32 milliseconds);
MXD_RTN_CODE_E MXD_API DTMB_SetDeviceMode(IN HMXDDEV hDevice, IN DEVICE_WORK_MODE_E eDeviceMode);
MXD_RTN_CODE_E MXD_API DTMB_CypCalibrate(IN HMXDDEV hDevice, IN MXD_U8 frmNumStart, IN MXD_U8 cypThd);
MXD_RTN_CODE_E MXD_API DTMB_UfoCalibrate(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_DownloadMtx(IN HMXDDEV hDevice, IN MXD_U32 sdramAddr, IN MXD_U8 *pMtxTable, IN MXD_U32 mtxLen);
MXD_RTN_CODE_E MXD_API DTMB_InitDevice(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_StartDevice(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_CheckTpsVal(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_IsSignalSynced(IN HMXDDEV hDevice, IN MXD_U32 milliseconds);
MXD_RTN_CODE_E MXD_API DTMB_StartStream(IN HMXDDEV hDevice, IN MXD_U8 tpsId);
MXD_RTN_CODE_E MXD_API DTMB_StopStream(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_PauseStream(IN HMXDDEV hDevice);
MXD_U32 MXD_API DTMB_GetSnr(IN HMXDDEV hDevice);
MXD_U32 MXD_API DTMB_GetRssi(IN HMXDDEV hDevice);
MXD_U32 MXD_API DTMB_GetBler(IN HMXDDEV hDevice);
MXD_U32 MXD_API DTMB_GetBer(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_GetSystemInfo(IN HMXDDEV hDevice, OUT DTMB_SYSTEM_INFO_S *psDtmbSystemInfo);
MXD_RTN_CODE_E MXD_API DTMB_GetServiceMap(IN HMXDDEV hDevice, OUT DTMB_SERVICE_MAP_S *psDtmbServiceMap);
MXD_RTN_CODE_E MXD_API DTMB_IsTpsOk(IN HMXDDEV hDevice, IN MXD_U32 milliseconds);
MXD_RTN_CODE_E MXD_API DTMB_ChangeToZif(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DTMB_IsSignalExist(IN HMXDDEV hDevice, IN MXD_S32 milliseconds);
MXD_U32 MXD_API DTMB_CalcCpp(IN MXD_S32 ifKhz, IN MXD_U8 ifRate);
MXD_RTN_CODE_E MXD_API DTMB_LoadEeprom(IN HMXDDEV hDevice, IN MXD_U32 sdramAddr);

/*
 * DDS Section
 */
MXD_RTN_CODE_E MXD_API DDS_ReadReg(IN HMXDDEV hDevice, IN MXD_U32 regAddr, OUT MXD_U8 *pRegVal);
MXD_RTN_CODE_E MXD_API DDS_WriteReg (IN HMXDDEV hDevice, IN MXD_U32 regAddr, IN MXD_U8 regVal);
MXD_RTN_CODE_E MXD_API DDS_ReadRegFields(IN HMXDDEV hDevice, IN MXD_U32 regAddr, IN MXD_U8 bitOffset, IN MXD_U8 bitCnt, OUT MXD_U8 *pRegVal);
MXD_RTN_CODE_E MXD_API DDS_WriteRegFields(IN HMXDDEV hDevice, IN MXD_U32 regAddr, IN MXD_U8 bitOffset, IN MXD_U8 bitCnt, IN MXD_U8 regVal);
MXD_RTN_CODE_E MXD_API DDS_BurstRead(IN HMXDDEV hDevice, IN MXD_U8 burstMode, IN MXD_U8 bufferAddr, IN MXD_U16 burstLen, OUT MXD_U8 *pBurstDataIn);

/*
 * SDRAM Section 
 */
#define SDRM_TEST_ADDRESS 0x000000
#define SDRAM_BURST_LENGTH_SET_1_VAL 0
#define SDRAM_BURST_LENGTH_SET_2_VAL 1
#define SDRAM_BURST_LENGTH_SET_4_VAL 2
#define SDRAM_BURST_LENGTH_SET_8_VAL 3
#define SDRAM_REFRESH_PERIOD_32 0
#define SDRAM_REFRESH_PERIOD_64 1
#define SDRAM_MISC_CAS_LAT_BIT 0x04
#define SDRAM_MISC_BURST_LEN_BIT 0x03
#define SDRAM_AUTO_INIT_BIT 0x1
#define SDRAM_AUTO_INIT_BIT_VAL 0x2
#define SDRAM_INIT_BEGIN_BIT 0x0
#define SDRAM_INIT_BEGIN_BIT_VAL 0x1
#define SDRAM_DIR_ACCESS_CONTROL_BIT 0x0
#define SDRAM_DIR_ACCESS_ENABLE_VAL 0x1
#define SDRAM_DIR_ACCESS_DISABLE_VAL 0x0
#define SDRAM_DIR_READ_VAL 0x2
#define SDRAM_DIR_WRITE_VAL 0x1

MXD_RTN_CODE_E MXD_API DDS_SetupSdramController( IN HMXDDEV hDevice );

/*
 * TS Port Section 
 */
#ifdef __I2C_TS_USED__
#define TS_TRANSFER_ENABLE_BIT 0
#define REFER_CLOCK_FREQ_13MHZ      12000
#define REFER_CLOCK_FREQ_9MHZ        9000
#define REFER_CLOCK_FREQ_4MHZ        4000
#define MP2TS_PARALLEL_SET			0x20
#define MP2TS_SERIAL_SET			0x00
#define MP2TS_CLKFREQ_QUA_MODE1	0x00	/*24.576MHz*/
#define MP2TS_CLKFREQ_QUA_MODE2	0x08	/*12.288MHz*/
#define MP2TS_CLKFREQ_QUA_MODE3	0x10	/* 6.144MHz */
#define MP2TS_CLKFREQ_QUA_MODE4	0x18	/* 3.072MHz */
#define MP2TS_MSB_SET 				0x00	/*msb is sent first*/
#define MP2TS_LSB_SET 				0x02	/*lsb is sent first*/
#define MP2TS_POSEDGE_SET			0x04	/*posedge */
#define MP2TS_NEGEDGE_SET			0x00	/*negedge*/
#define MP2TS_ENABLE_SET			0x01	/*enable mp2ts */
#define MP2TS_DISABLE_SET			0x00	/*disable mp2ts*/

MXD_RTN_CODE_E MXD_API DDS_SetupMxdMp2ts ( IN HMXDDEV hDevice );
MXD_RTN_CODE_E MXD_API DDS_EnableMxdMp2tsTx ( IN HMXDDEV hDevice );
MXD_RTN_CODE_E MXD_API DDS_DisableMxdMp2tsTx  (IN HMXDDEV hDevice );
#endif /* end of #ifdef __I2C_TS_USED__ */

/*
 * SPI Section 
 */
#ifdef __SPI_USED__
/* #define __SPI_CHECK__ */
#define OCR 0xFFFF00
#define SPI_MAC_RESET_REG 0x06
#define LENGTH_CMD53_NCR_R5_NAC (6+8+2+8)
#define INT_USE_SPI_MAC 0

MXD_RTN_CODE_E MXD_API DDS_SetupMxdSpi(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DDS_StopMxdSpi(IN HMXDDEV hDevice);
MXD_RTN_CODE_E MXD_API DDS_MxdSpiCmd52(IN HMXDDEV hDevice, IN MXD_U8 rwIndicator, IN MXD_U8 regFuncNum, IN MXD_U32 regAddr, INOUT MXD_U8 *pRegVal);
MXD_RTN_CODE_E MXD_API DDS_MxdSpiCmd53(IN HMXDDEV hDevice, IN MXD_U8 burstMode, IN MXD_U32 bufferAddr, IN MXD_U16 byteCnt, OUT MXD_U8 *pBurstDataIn);
MXD_RTN_CODE_E MXD_API DDS_MasterSpiTxRx(IN HMXDDEV hDevice, IN MXD_U32 trxLen, IN MXD_U8 *pDataOut, OUT MXD_U8 *pDataIn);
#endif /* end of #ifdef __SPI_USED__ */

/*
 * UTIL Section 
 */
MXD_U8 MXD_API UTIL_BitSet(IN MXD_U8 inputVal, IN MXD_U8 bitOffset, IN MXD_U8 bitCnt, IN MXD_U8 setVal);
MXD_U8 UTIL_Dec2Bin(MXD_U8 algoVal);

/*
 * OAL Section
 */
#define DEBUG_TRACE_LEVEL 2
#define MXD_ULTRA_TRACE 1
#define MXD_MAX_TRACE 2
#define MXD_MIN_TRACE 3
VOID MXD_API OAL_DebugPrint( IN MXD_U8 trace, IN CONST MXD_CHAR* dbgOutput, ... );

MXD_RTN_CODE_E MXD_API OAL_Sleep(IN MXD_U32 milliSeconds);
VOID *OAL_Memcpy(VOID * pDest, CONST VOID *pSrc, MXD_U32 size);
VOID *OAL_Memset(VOID * pDest, MXD_U8 value, MXD_U32 size);

#ifdef __cplusplus
}
#endif
 
#endif /* __MXD_SDK_API_H__ */
 
/* end of mxd_sdk_api.h */