?? validatebaudrate.lis
字號:
.module ValidateBaudRate.c
.area text(rom, con, rel)
0000 .dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
.area vector(rom, abs)
.org 44
002C 0C940000 jmp _uart_rx_isr
.area text(rom, con, rel)
0000 .dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
.area data(ram, con, rel)
0000 .dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
0000 _rec_head::
0000 .blkb 2
.area idata
0000 0000 .word 0
.area data(ram, con, rel)
0002 .dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
0002 .dbsym e rec_head _rec_head I
0002 _rec_tail::
0002 .blkb 2
.area idata
0002 0000 .word 0
.area data(ram, con, rel)
0004 .dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
0004 .dbsym e rec_tail _rec_tail I
.area text(rom, con, rel)
0000 .dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
0000 .dbfunc e uart_rx_isr _uart_rx_isr fV
.even
0000 _uart_rx_isr::
0000 2A92 st -y,R2
0002 3A92 st -y,R3
0004 8A93 st -y,R24
0006 9A93 st -y,R25
0008 EA93 st -y,R30
000A FA93 st -y,R31
000C 2FB6 in R2,0x3f
000E 2A92 st -y,R2
0010 .dbline -1
0010 .dbline 56
0010 ; //ICC-AVR application builder : 2009-4-7 20:13:28
0010 ; // Target : M16
0010 ; // Crystal: 16.000Mhz
0010 ;
0010 ; // Title: ValidateBaudRate.c
0010 ; // Operation:
0010 ; // This program make echo to PC sending in Baudrate 38400
0010 ; // it receives sending from PC and sends the received one back to PC
0010 ; // The LED group1 (the left one) makes counting on received data
0010 ; // The LED group2 display the received data in binary
0010 ; // Attention: A terminal program "Tera Term Pro" is contained in CD
0010 ; // for PC to communicate with the AVR Study Board
0010 ;
0010 ; /* UCSRA: Control & Status Register A
0010 ; b7-RXC: USART receive complete
0010 ; b6-TXC: USART transmit complete
0010 ; b5-UDRE: USART Data register empty
0010 ; b4-FE: Frame Error
0010 ; b3-DOR: Data overtun
0010 ; b2-PE: Parity error
0010 ; b1-U2X: double the USART transmission speed
0010 ; b0-MPCM: multi-processor communication mode
0010 ;
0010 ; USARB
0010 ; * b7-RXCIE: RX complete interrupt enable
0010 ; b6-TXCIE: TX complete interrupt enable
0010 ; b5-UDRIE: USART data register empty interrupt enable
0010 ; * b4-RXEN: Receiver enable
0010 ; * b3-TXEN: Transmitter enable
0010 ; b2-UCSZ2: chracter size ------->0
0010 ; b1-RXB8 receive data bit 8
0010 ; b0-TXB8: Transmit data 8
0010 ;
0010 ; UCSRC
0010 ; * b7-URSEL: register select 0/UBRRH, 1/UCSRC
0010 ; b6-UMSEL: USART mode select 0/Asyn 1/Synchronous
0010 ; b5-UPM1: -------- Parity mode 00/disable, 01 reserved
0010 ; b4-UPM0: -------- 10 even, 11 odd
0010 ; b3-USBS: stop bit selection 0/1-bit, 1/2-bit
0010 ; * b2-UCSZ1 --------> 1
0010 ; * b1-UCSZ0 --------> 1
0010 ; b0-UCPOL: clock polarity 0 rising XCK edge, 1 falling XCK edge
0010 ; */
0010 ;
0010 ;
0010 ; #include <iom16v.h>
0010 ; #include <macros.h>
0010 ;
0010 ; #pragma interrupt_handler uart_rx_isr: 12//the interrupt of RX finish
0010 ;
0010 ; unsigned char RecBuf[40];
0010 ; int rec_head=0, rec_tail=0;
0010 ; unsigned char rec_data;
0010 ;
0010 ; void uart_rx_isr(void)
0010 ; {
0010 .dbline 57
0010 ; RecBuf[rec_head]=UDR;
0010 80E0 ldi R24,<_RecBuf
0012 90E0 ldi R25,>_RecBuf
0014 E0910000 lds R30,_rec_head
0018 F0910100 lds R31,_rec_head+1
001C E80F add R30,R24
001E F91F adc R31,R25
0020 2CB0 in R2,0xc
0022 2082 std z+0,R2
0024 .dbline 58
0024 ; rec_head++;
0024 80910000 lds R24,_rec_head
0028 90910100 lds R25,_rec_head+1
002C 0196 adiw R24,1
002E 90930100 sts _rec_head+1,R25
0032 80930000 sts _rec_head,R24
0036 .dbline 59
0036 ; if(rec_head>=40)
0036 8832 cpi R24,40
0038 E0E0 ldi R30,0
003A 9E07 cpc R25,R30
003C 34F0 brlt L2
003E X0:
003E .dbline 60
003E ; rec_head=0;
003E 2224 clr R2
0040 3324 clr R3
0042 30920100 sts _rec_head+1,R3
0046 20920000 sts _rec_head,R2
004A L2:
004A .dbline -2
004A L1:
004A .dbline 0 ; func end
004A 2990 ld R2,y+
004C 2FBE out 0x3f,R2
004E F991 ld R31,y+
0050 E991 ld R30,y+
0052 9991 ld R25,y+
0054 8991 ld R24,y+
0056 3990 ld R3,y+
0058 2990 ld R2,y+
005A 1895 reti
005C .dbend
005C .dbfunc e port_init _port_init fV
.even
005C _port_init::
005C .dbline -1
005C .dbline 64
005C ; }
005C ;
005C ; void port_init(void)
005C ; {
005C .dbline 65
005C ; DDRA = 0xFF; //set PortA output
005C 8FEF ldi R24,255
005E 8ABB out 0x1a,R24
0060 .dbline 66
0060 ; DDRB = 0xff; //set PORTB output
0060 87BB out 0x17,R24
0062 .dbline 67
0062 ; DDRC = 0x00; //set PORTC output
0062 2224 clr R2
0064 24BA out 0x14,R2
0066 .dbline 68
0066 ; PORTC = 0xff;
0066 85BB out 0x15,R24
0068 .dbline 69
0068 ; DDRD = 0x7f; //set PD.7 input for RX ？
0068 8FE7 ldi R24,127
006A 81BB out 0x11,R24
006C .dbline -2
006C L4:
006C .dbline 0 ; func end
006C 0895 ret
006E .dbend
006E .dbfunc e USART_init _USART_init fV
.even
006E _USART_init::
006E .dbline -1
006E .dbline 74
006E ; //PD.0 is RX.
006E ; }
006E ;
006E ; void USART_init(void)
006E ; {
006E .dbline 75
006E ; UCSRB=0x00;
006E 2224 clr R2
0070 2AB8 out 0xa,R2
0072 .dbline 76
0072 ; UCSRA=0x00;
0072 2BB8 out 0xb,R2
0074 .dbline 77
0074 ; UCSRB=0b10011000; //b7: RXCIE enabeled, b4: RXEN enabled, B3: TXEN enabled
0074 88E9 ldi R24,152
0076 8AB9 out 0xa,R24
0078 .dbline 78
0078 ; UBRRH=0x00; //
0078 20BC out 0x20,R2
007A .dbline 82
007A ; //Crystal=16MHx
007A ; //UBRRL=103; //Bausdrate=9600 tested work fine
007A ; //UBRRL=51; //Baudrate=19200 tested work fine
007A ; UBRRL=25; //Baudrate=38400 tested work fine //v7.14版本在這里代碼生成器犯低級錯誤；
007A 89E1 ldi R24,25
007C 89B9 out 0x9,R24
007E .dbline 85
007E ; //eg:in the application bulider,UBRR=25,however,it can bulid UBRR=19.
007E ; //UBRRL=8; //Baurate=115200 tested work fine
007E ; UCSRC=0b10000110; //Asyn, No parity, 1-stop, 8-bit, rising edge
007E 86E8 ldi R24,134
0080 80BD out 0x20,R24
0082 .dbline 87
0082 ; // memset(RecBuf, 0, sizeof(RecBuf));
0082 ; rec_head=0;
0082 3324 clr R3
0084 30920100 sts _rec_head+1,R3
0088 20920000 sts _rec_head,R2
008C .dbline 88
008C ; rec_tail=0;
008C 30920300 sts _rec_tail+1,R3
0090 20920200 sts _rec_tail,R2
0094 .dbline -2
0094 L5:
0094 .dbline 0 ; func end
0094 0895 ret
0096 .dbend
0096 .dbfunc e delay _delay fV
0096 ; i -> R20,R21
0096 ; j -> R22,R23
0096 ; count -> R16,R17
.even
0096 _delay::
0096 0E940000 xcall push_xgsetF000
009A .dbline -1
009A .dbline 92
009A ; }
009A ;
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