.module ValidateBaudRate.c
	.area text(rom, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
	.area vector(rom, abs)
	.org 44
	jmp _uart_rx_isr
	.area text(rom, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
	.area data(ram, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
_KeyMark::
	.blkb 1
	.area idata
	.byte 0
	.area data(ram, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
	.dbsym e KeyMark _KeyMark c
_rec_head::
	.blkb 2
	.area idata
	.word 0
	.area data(ram, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
	.dbsym e rec_head _rec_head I
_rec_tail::
	.blkb 2
	.area idata
	.word 0
	.area data(ram, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
	.dbsym e rec_tail _rec_tail I
	.area text(rom, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
	.dbfunc e uart_rx_isr _uart_rx_isr fV
	.even
_uart_rx_isr::
	st -y,R2
	st -y,R3
	st -y,R24
	st -y,R25
	st -y,R30
	st -y,R31
	in R2,0x3f
	st -y,R2
	.dbline -1
	.dbline 67
; //ICC-AVR application builder : 2009-4-7 20:13:28
; // Target : M16
; // Crystal: 16.000Mhz
; 
; // Title: 		ValidateBaudRate.c
; // Operation:
; // 			   1> This program make echo to PC sending in Baudrate 38400
; //			   2> AVR Study Board sends Data"from FF to 00" to PC in the SComAssistant.
; //             3> The display will be showed when the key k7 is pressed.
; // Attention:  
; //             1> HEX must be setuped to show in the SComAssistant.
; //             
; 
; /* UCSRA: Control & Status Register A
;    b7-RXC: 	USART receive complete
;    b6-TXC: 	USART transmit complete
;    b5-UDRE:	USART Data register empty
;    b4-FE:	Frame Error
;    b3-DOR:  Data overtun
;    b2-PE: 	Parity error
;    b1-U2X: 	double the USART transmission speed
;    b0-MPCM: multi-processor communication mode
;    
;    USARB
; *  b7-RXCIE: RX complete interrupt enable
;    b6-TXCIE: TX complete interrupt enable
;    b5-UDRIE: USART data register empty interrupt enable
; *  b4-RXEN:	 Receiver enable
; *  b3-TXEN:  Transmitter enable
;    b2-UCSZ2: chracter size     	 ------->0
;    b1-RXB8	 receive data bit 8
;    b0-TXB8:	 Transmit data 8
;    
;    UCSRC
; *  b7-URSEL: register select   	 0/UBRRH,	  1/UCSRC
;    b6-UMSEL: USART mode select 	 0/Asyn		  1/Synchronous
;    b5-UPM1:  -------- Parity mode 00/disable, 01 reserved
;    b4-UPM0:	 -------- 		 	  10 even,	  11 odd 
;    b3-USBS:	stop bit selection 0/1-bit, 1/2-bit
; *  b2-UCSZ1	 		  	   	   --------> 1
; *  b1-UCSZ0  				   --------> 1
;    b0-UCPOL: clock polarity	  0 rising XCK edge, 1 falling XCK edge  
; */
; 
; #define  uchar unsigned char
; #define  uint  unsigned int
; #define K1 0x01        //按鍵K0與PC0相連 啟動(dòng)鍵（start)
; #define K0 0x02        //按鍵K1與PC1相連 調(diào)節(jié)鍵（adjust）
; #define K6 BIT(6)      //按鍵K6與PC6相連 休眠鍵（sleep）
; #define K7 BIT(7)      //按鍵K7與PC7相連 暫停鍵（pause）
; #define dig0 (1<<6)    //推薦用這種形式，簡(jiǎn)單形象
; #define dig1 (1<<7)
; #define LED PORTD
; #define LED1 PORTA
; #define PressKey (PINC&K7)==0
; 
; #include <iom16v.h>
; #include <macros.h>
; 
; #pragma interrupt_handler uart_rx_isr: 12//the interrupt of RX finish
; 
; unsigned char RecBuf[40],KeyMark=0;
; int rec_head=0, rec_tail=0;
; unsigned char rec_data;
; 
; void uart_rx_isr(void)
; {
	.dbline 68
;  RecBuf[rec_head]=UDR;
	ldi R24,<_RecBuf
	ldi R25,>_RecBuf
	lds R30,_rec_head
	lds R31,_rec_head+1
	add R30,R24
	adc R31,R25
	in R2,0xc
	std z+0,R2
	.dbline 69
;  rec_head++;
	lds R24,_rec_head
	lds R25,_rec_head+1
	adiw R24,1
	sts _rec_head+1,R25
	sts _rec_head,R24
	.dbline 70
;  if(rec_head>=40)
	cpi R24,40
	ldi R30,0
	cpc R25,R30
	brlt L2
X0:
	.dbline 71
;  	rec_head=0;
	clr R2
	clr R3
	sts _rec_head+1,R3
	sts _rec_head,R2
L2:
	.dbline -2
L1:
	.dbline 0 ; func end
	ld R2,y+
	out 0x3f,R2
	ld R31,y+
	ld R30,y+
	ld R25,y+
	ld R24,y+
	ld R3,y+
	ld R2,y+
	reti
	.dbend
	.dbfunc e port_init _port_init fV
	.even
_port_init::
	.dbline -1
	.dbline 75
; }
; 
; void port_init(void)
; {
	.dbline 76
;  DDRA  = 0xFF;		//set PortA output
	ldi R24,255
	out 0x1a,R24
	.dbline 77
;  DDRB  = 0xff;		//set PORTB output
	out 0x17,R24
	.dbline 78
;  DDRC  = 0x00;		//set PORTC output
	clr R2
	out 0x14,R2
	.dbline 79
;  PORTC = 0xff;
	out 0x15,R24
	.dbline 80
;  DDRD  = 0x7f;		//set PD.7 input for RX ？
	ldi R24,127
	out 0x11,R24
	.dbline -2
L4:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e USART_init _USART_init fV
	.even
_USART_init::
	.dbline -1
	.dbline 85
;                     //PD.0 is RX.
; }
; 
; void USART_init(void)
; {
	.dbline 86
;  UCSRB=0x00;
	clr R2
	out 0xa,R2
	.dbline 87
;  UCSRA=0x00;
	out 0xb,R2
	.dbline 88
;  UCSRB=0b10011000;	 //b7: RXCIE enabeled, b4: RXEN enabled, B3: TXEN enabled
	ldi R24,152
	out 0xa,R24
	.dbline 89
;  UBRRH=0x00;		 //
	out 0x20,R2
	.dbline 93
;  					 //Crystal=16MHx
;  //UBRRL=103;		 //Bausdrate=9600 tested work fine
;  //UBRRL=51;		 //Baudrate=19200 tested work fine
;  UBRRL=25;		 	 //Baudrate=38400 tested work fine //v7.14版本在這里代碼生成器犯低級(jí)錯(cuò)誤；
	ldi R24,25
	out 0x9,R24
	.dbline 96
;  //eg:in the application bulider,UBRR=25,however,it can bulid UBRR=19.
;  //UBRRL=8;	 		 //Baurate=115200 tested work fine
;  UCSRC=0b10000110;	 //Asyn, No parity, 1-stop, 8-bit, rising edge
	ldi R24,134
	out 0x20,R24
	.dbline 98
; // memset(RecBuf, 0, sizeof(RecBuf));
;  rec_head=0;
	clr R3
	sts _rec_head+1,R3
	sts _rec_head,R2
	.dbline 99
;  rec_tail=0;
	sts _rec_tail+1,R3
	sts _rec_tail,R2
	.dbline -2
L5:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e delay_ms _delay_ms fV
;              i -> R20,R21
;              j -> R22,R23
;          count -> R16,R17
	.even
_delay_ms::
	xcall push_xgsetF000
	.dbline -1
	.dbline 103
; } 
; 
; void delay_ms(int count)
; {
	.dbline 105
;  int i, j;
;  for(i=count; i>0; i--)
	movw R20,R16
	xjmp L10
L7:
	.dbline 106
;     for(j=500; j>0; j--)
	ldi R22,500
	ldi R23,1
L11:
	.dbline 107
; 	   ;
L12:
	.dbline 106
	subi R22,1
	sbci R23,0
	.dbline 106
	clr R2
	clr R3
	cp R2,R22
	cpc R3,R23
	brlt L11
X1:
L8:
	.dbline 105
	subi R20,1
	sbci R21,0
L10:
	.dbline 105
	clr R2
	clr R3
	cp R2,R20
	cpc R3,R21
	brlt L7
X2:
	.dbline -2
L6:
	.dbline 0 ; func end
	xjmp pop_xgsetF000
	.dbsym r i 20 I
	.dbsym r j 22 I
	.dbsym r count 16 I
	.dbend
	.dbfunc e transmit _transmit fV
;          abyte -> R16
	.even
_transmit::
	.dbline -1
	.dbline 111
; }
; 
; void transmit(unsigned char abyte)
; {
	.dbline 112
;  UDR=abyte;
	out 0xc,R16
L16:
	.dbline 114
;  while(!(UCSRA&0b01000000))	//b6=1 TXE	,it quit when transmission finish.
; 	  ;
L17:
	.dbline 113
	sbis 0xb,6
	rjmp L16
X3:
	.dbline -2
L15:
	.dbline 0 ; func end
	ret
	.dbsym r abyte 16 c
	.dbend
	.dbfunc e main _main fV
;          dswin -> R10,R11
;       SendData -> R20
	.even
_main::
	.dbline -1
	.dbline 119
; }
; 
; //*****************************************************************
; void main(void)
; {
	.dbline 122
; // unsigned char outa=0b01010101, outb=0b10101010, outc=0x00, outd=0x00;
;  int dswin;
;  unsigned char SendData=0;
	clr R20
	.dbline 123
;  port_init();
	xcall _port_init
	.dbline 124
;  USART_init();
	xcall _USART_init
	.dbline 125
;  SEI();
	sei
	xjmp L21
L20:
	.dbline 128
;  
;  while(1)
;    {
	.dbline 129
;     WDR();				  	//Watchdog reset
	wdr
	.dbline 130
; 	if(rec_head!=rec_tail)
	lds R2,_rec_tail
	lds R3,_rec_tail+1
	lds R4,_rec_head
	lds R5,_rec_head+1
	cp R4,R2
	cpc R5,R3
	breq L23
X4:
	.dbline 131
; 	   {
	.dbline 132
; 	    rec_data=RecBuf[rec_tail];	//read data from head and write data at tail
	ldi R24,<_RecBuf
	ldi R25,>_RecBuf
	movw R30,R2
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	sts _rec_data,R2
	.dbline 133
; 		rec_tail++;
	lds R24,_rec_tail
	lds R25,_rec_tail+1
	adiw R24,1
	sts _rec_tail+1,R25
	sts _rec_tail,R24
	.dbline 136
; 		//rec_data=RecBuf[rec_tail++]; //you can amend the sentences above two like that
; 		//i++; show that first use it,then add it.
; 		if(rec_tail>=40)	//make up circular queue
	cpi R24,40
	ldi R30,0
	cpc R25,R30
	brlt L25
X5:
	.dbline 137
; 		   rec_tail=0;
	clr R2
	clr R3
	sts _rec_tail+1,R3
	sts _rec_tail,R2
L25:
	.dbline 139
; 		   
; 		dswin=rec_head<<2;	//the lowest 2 bit of PORTD are RXD and TXD.
	lds R10,_rec_head
	lds R11,_rec_head+1
	lsl R10
	rol R11
	lsl R10
	rol R11
	.dbline 140
; 	    PORTD=dswin;        //The two ports are occupied,so it need "<<2".
	out 0x12,R10
	.dbline 141
; 		PORTA=rec_data;     //rec_head++,so it can stand for the number of received data.
	lds R2,_rec_data
	out 0x1b,R2
	.dbline 142
; 		transmit(rec_data);
	mov R16,R2
	xcall _transmit
	.dbline 143
; 		if(rec_data==13)	//★??
	lds R24,_rec_data
	cpi R24,13
	brne L27
X6:
	.dbline 144
; 			transmit(10);
	ldi R16,10
	xcall _transmit
L27:
	.dbline 145
; 	   } 
L23:
	.dbline 146
;     if(PressKey&&!KeyMark)    //clamping using state bit
	sbic 0x13,7
	rjmp L29
X7:
	lds R2,_KeyMark
	tst R2
	brne L29
X8:
	.dbline 147
;     {
	.dbline 148
;       delay_ms(20); 
	ldi R16,20
	ldi R17,0
	xcall _delay_ms
	.dbline 149
;       if(PressKey)
	sbic 0x13,7
	rjmp L30
X9:
	.dbline 150
;       {
	.dbline 151
;         KeyMark=1;
	ldi R24,1
	sts _KeyMark,R24
	.dbline 152
;         SendData=0xFF;        
	ldi R20,255
	.dbline 153
;       }  
	.dbline 154
;     }
	xjmp L30
L29:
	.dbline 155
;     else if(!PressKey)
	sbic 0x13,7
	rjmp L35
X10:
	ldi R22,1
	ldi R23,0
	xjmp L36
L35:
	clr R22
	clr R23
L36:
	cpi R22,0
	cpc R22,R23
	brne L33
X11:
	.dbline 156
;     KeyMark=0;
	clr R2
	sts _KeyMark,R2
L33:
L30:
	.dbline 158
; //    while(PressKey);        //clamping using endless loop on conditionZ
;      if(SendData)
	tst R20
	breq L37
X12:
	.dbline 159
;      {
L39:
	.dbline 160
;          while(!(UCSRA&(1<<UDRE)));
L40:
	.dbline 160
	sbis 0xb,5
	rjmp L39
X13:
	.dbline 161
;          UDR=SendData;
	out 0xc,R20
	.dbline 162
;          SendData--;
	dec R20
	.dbline 163
;      }
L37:
	.dbline 165
; 
;  }
L21:
	.dbline 127
	xjmp L20
X14:
	.dbline -2
L19:
	.dbline 0 ; func end
	ret
	.dbsym r dswin 10 I
	.dbsym r SendData 20 c
	.dbend
	.area bss(ram, con, rel)
	.dbfile D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
_rec_data::
	.blkb 1
	.dbsym e rec_data _rec_data c
_RecBuf::
	.blkb 40
	.dbsym e RecBuf _RecBuf A[40:40]c
; }