__start:
__text_start:
      2C E5CF      LDI	R28,0x5F
      2D E0D4      LDI	R29,4
      2E BFCD      OUT	0x3D,R28
      2F BFDE      OUT	0x3E,R29
      30 51CE      SUBI	R28,0x1E
      31 40D0      SBCI	R29,0
      32 EA0A      LDI	R16,0xAA
      33 8308      STD	Y+0,R16
      34 2400      CLR	R0
      35 E6E4      LDI	R30,0x64
      36 E0F0      LDI	R31,0
      37 E010      LDI	R17,0
      38 38ED      CPI	R30,0x8D
      39 07F1      CPC	R31,R17
      3A F011      BEQ	0x003D
      3B 9201      ST	R0,Z+
      3C CFFB      RJMP	0x0038
      3D 8300      STD	Z+0,R16
      3E E5E4      LDI	R30,0x54
      3F E0F0      LDI	R31,0
      40 E6A0      LDI	R26,0x60
      41 E0B0      LDI	R27,0
      42 E010      LDI	R17,0
      43 E000      LDI	R16,0
      44 BF0B      OUT	0x3B,R16
      45 35E8      CPI	R30,0x58
      46 07F1      CPC	R31,R17
      47 F021      BEQ	0x004C
      48 95C8      LPM
      49 9631      ADIW	R30,1
      4A 920D      ST	R0,X+
      4B CFF9      RJMP	0x0045
      4C 940E 00B4 CALL	_main
_exit:
      4E CFFF      RJMP	_exit
_uart_rx_isr:
      4F 922A      ST	R2,-Y
      50 923A      ST	R3,-Y
      51 938A      ST	R24,-Y
      52 939A      ST	R25,-Y
      53 93EA      ST	R30,-Y
      54 93FA      ST	R31,-Y
      55 B62F      IN	R2,0x3F
      56 922A      ST	R2,-Y
FILE: D:\MYDOCU~1\EXPRIMENT\ICC\UART\ValidateBaudRate\ValidateBaudRate.c
(0001) //ICC-AVR application builder : 2009-4-7 20:13:28
(0002) // Target : M16
(0003) // Crystal: 16.000Mhz
(0004) 
(0005) // Title: 		ValidateBaudRate.c
(0006) // Operation:
(0007) // 			    This program make echo to PC sending in Baudrate 38400
(0008) //					 it receives sending from PC and sends the received one back to PC
(0009) //				The LED group1 (the left one) makes counting on received data
(0010) //				The LED group2 display the received data in binary
(0011) // Attention:	A terminal program "Tera Term Pro" is contained in CD 
(0012) // 				  for PC to communicate with the AVR Study Board	
(0013) 
(0014) /* UCSRA: Control & Status Register A
(0015)    b7-RXC: 	USART receive complete
(0016)    b6-TXC: 	USART transmit complete
(0017)    b5-UDRE:	USART Data register empty
(0018)    b4-FE:	Frame Error
(0019)    b3-DOR:  Data overtun
(0020)    b2-PE: 	Parity error
(0021)    b1-U2X: 	double the USART transmission speed
(0022)    b0-MPCM: multi-processor communication mode
(0023)    
(0024)    USARB
(0025) *  b7-RXCIE: RX complete interrupt enable
(0026)    b6-TXCIE: TX complete interrupt enable
(0027)    b5-UDRIE: USART data register empty interrupt enable
(0028) *  b4-RXEN:	 Receiver enable
(0029) *  b3-TXEN:  Transmitter enable
(0030)    b2-UCSZ2: chracter size     	 ------->0
(0031)    b1-RXB8	 receive data bit 8
(0032)    b0-TXB8:	 Transmit data 8
(0033)    
(0034)    UCSRC
(0035) *  b7-URSEL: register select   	 0/UBRRH,	  1/UCSRC
(0036)    b6-UMSEL: USART mode select 	 0/Asyn		  1/Synchronous
(0037)    b5-UPM1:  -------- Parity mode 00/disable, 01 reserved
(0038)    b4-UPM0:	 -------- 		 	  10 even,	  11 odd 
(0039)    b3-USBS:	stop bit selection 0/1-bit, 1/2-bit
(0040) *  b2-UCSZ1	 		  	   	   --------> 1
(0041) *  b1-UCSZ0  				   --------> 1
(0042)    b0-UCPOL: clock polarity	  0 rising XCK edge, 1 falling XCK edge  
(0043) */
(0044) 
(0045) 
(0046) #include <iom16v.h>
(0047) #include <macros.h>
(0048) 
(0049) #pragma interrupt_handler uart_rx_isr: 12//the interrupt of RX finish
(0050) 
(0051) unsigned char RecBuf[40];
(0052) int rec_head=0, rec_tail=0;
(0053) unsigned char rec_data;
(0054) 
(0055) void uart_rx_isr(void)
(0056) {
(0057)  RecBuf[rec_head]=UDR;
      57 E685      LDI	R24,0x65
      58 E090      LDI	R25,0
      59 91E0 0060 LDS	R30,rec_head
      5B 91F0 0061 LDS	R31,rec_head+1
      5D 0FE8      ADD	R30,R24
      5E 1FF9      ADC	R31,R25
      5F B02C      IN	R2,0x0C
      60 8220      STD	Z+0,R2
(0058)  rec_head++;
      61 9180 0060 LDS	R24,rec_head
      63 9190 0061 LDS	R25,rec_head+1
      65 9601      ADIW	R24,1
      66 9390 0061 STS	rec_head+1,R25
      68 9380 0060 STS	rec_head,R24
(0059)  if(rec_head>=40)
      6A 3288      CPI	R24,0x28
      6B E0E0      LDI	R30,0
      6C 079E      CPC	R25,R30
      6D F034      BLT	0x0074
(0060)  	rec_head=0;			  
      6E 2422      CLR	R2
      6F 2433      CLR	R3
      70 9230 0061 STS	rec_head+1,R3
      72 9220 0060 STS	rec_head,R2
      74 9029      LD	R2,Y+
      75 BE2F      OUT	0x3F,R2
      76 91F9      LD	R31,Y+
      77 91E9      LD	R30,Y+
      78 9199      LD	R25,Y+
      79 9189      LD	R24,Y+
      7A 9039      LD	R3,Y+
      7B 9029      LD	R2,Y+
      7C 9518      RETI
(0061) }
(0062) 
(0063) void port_init(void)
(0064) {
(0065)  DDRA  = 0xFF;		//set PortA output
_port_init:
      7D EF8F      LDI	R24,0xFF
      7E BB8A      OUT	0x1A,R24
(0066)  DDRB  = 0xff;		//set PORTB output
      7F BB87      OUT	0x17,R24
(0067)  DDRC  = 0x00;		//set PORTC output
      80 2422      CLR	R2
      81 BA24      OUT	0x14,R2
(0068)  PORTC = 0xff;
      82 BB85      OUT	0x15,R24
(0069)  DDRD  = 0x7f;		//set PD.7 input for RX ？
      83 E78F      LDI	R24,0x7F
      84 BB81      OUT	0x11,R24
      85 9508      RET
(0070)                     //PD.0 is RX.
(0071) }
(0072) 
(0073) void USART_init(void)
(0074) {
(0075)  UCSRB=0x00;
_USART_init:
      86 2422      CLR	R2
      87 B82A      OUT	0x0A,R2
(0076)  UCSRA=0x00;
      88 B82B      OUT	0x0B,R2
(0077)  UCSRB=0b10011000;	 //b7: RXCIE enabeled, b4: RXEN enabled, B3: TXEN enabled
      89 E988      LDI	R24,0x98
      8A B98A      OUT	0x0A,R24
(0078)  UBRRH=0x00;		 //
      8B BC20      OUT	0x20,R2
(0079)  					 //Crystal=16MHx
(0080)  //UBRRL=103;		 //Bausdrate=9600 tested work fine
(0081)  //UBRRL=51;		 //Baudrate=19200 tested work fine
(0082)  UBRRL=25;		 	 //Baudrate=38400 tested work fine //v7.14版本在這里代碼生成器犯低級錯誤；
      8C E189      LDI	R24,0x19
      8D B989      OUT	0x09,R24
(0083)  //eg:in the application bulider,UBRR=25,however,it can bulid UBRR=19.
(0084)  //UBRRL=8;	 		 //Baurate=115200 tested work fine
(0085)  UCSRC=0b10000110;	 //Asyn, No parity, 1-stop, 8-bit, rising edge
      8E E886      LDI	R24,0x86
      8F BD80      OUT	0x20,R24
(0086) // memset(RecBuf, 0, sizeof(RecBuf));
(0087)  rec_head=0;
      90 2433      CLR	R3
      91 9230 0061 STS	rec_head+1,R3
      93 9220 0060 STS	rec_head,R2
(0088)  rec_tail=0;
      95 9230 0063 STS	rec_tail+1,R3
      97 9220 0062 STS	rec_tail,R2
      99 9508      RET
_delay:
  i                    --> R20
  j                    --> R22
  count                --> R16
      9A 940E 00FC CALL	push_xgsetF000
(0089) } 
(0090) 
(0091) void delay(int count)
(0092) {
(0093)  int i, j;
(0094)  for(i=count; i>0; i--)
      9C 01A8      MOVW	R20,R16
      9D C00B      RJMP	0x00A9
(0095)     for(j=10; j>0; j--)
      9E E06A      LDI	R22,0xA
      9F E070      LDI	R23,0
      A0 5061      SUBI	R22,1
      A1 4070      SBCI	R23,0
      A2 2422      CLR	R2
      A3 2433      CLR	R3
      A4 1626      CP	R2,R22
      A5 0637      CPC	R3,R23
      A6 F3CC      BLT	0x00A0
      A7 5041      SUBI	R20,1
      A8 4050      SBCI	R21,0
      A9 2422      CLR	R2
      AA 2433      CLR	R3
      AB 1624      CP	R2,R20
      AC 0635      CPC	R3,R21
      AD F384      BLT	0x009E
      AE 940C 0101 JMP	pop_xgsetF000
(0096) 	   ;
(0097) }
(0098) 
(0099) void transmit(unsigned char abyte)
(0100) {
(0101)  UDR=abyte;
_transmit:
  abyte                --> R16
      B0 B90C      OUT	0x0C,R16
(0102)  while(!(UCSRA&0b01000000))	//b6=1 TXE	,it quit when transmission finish.
      B1 9B5E      SBIS	0x0B,6
      B2 CFFE      RJMP	0x00B1
      B3 9508      RET
(0103) 	  ;
(0104) }
(0105) 
(0106) //*****************************************************************
(0107) void main(void)
(0108) {
(0109) // unsigned char outa=0b01010101, outb=0b10101010, outc=0x00, outd=0x00;
(0110)  int dswin;
(0111)  unsigned char SendData=0xFF;
_main:
  dswin                --> R10
  SendData             --> R20
      B4 EF4F      LDI	R20,0xFF
(0112)  port_init();
      B5 DFC7      RCALL	_port_init
(0113)  USART_init();
      B6 DFCF      RCALL	_USART_init
(0114)  SEI();
      B7 9478      BSET	7
(0115)  do
(0116)  {
(0117)      while(!(UCSRA&(1<<UDRE)));
      B8 9B5D      SBIS	0x0B,5
      B9 CFFE      RJMP	0x00B8
(0118)      UDR=SendData;
      BA B94C      OUT	0x0C,R20
(0119)      SendData--;
      BB 954A      DEC	R20
(0120)  }
(0121)  while(SendData!=0xFF);
      BC 3F4F      CPI	R20,0xFF
      BD F7D1      BNE	0x00B8
      BE C03B      RJMP	0x00FA
(0122)  while(1)
(0123)    {
(0124)     WDR();				  	//Watchdog reset
      BF 95A8      WDR
(0125) 	if(rec_head!=rec_tail)
      C0 9020 0062 LDS	R2,rec_tail
      C2 9030 0063 LDS	R3,rec_tail+1
      C4 9040 0060 LDS	R4,rec_head
      C6 9050 0061 LDS	R5,rec_head+1
      C8 1442      CP	R4,R2
      C9 0453      CPC	R5,R3
      CA F179      BEQ	0x00FA
(0126) 	   {
(0127) 	    rec_data=RecBuf[rec_tail];	//read data from head and write data at tail
      CB E685      LDI	R24,0x65
      CC E090      LDI	R25,0
      CD 01F1      MOVW	R30,R2
      CE 0FE8      ADD	R30,R24
      CF 1FF9      ADC	R31,R25
      D0 8020      LDD	R2,Z+0
      D1 9220 0064 STS	rec_data,R2
(0128) 		rec_tail++;
      D3 9180 0062 LDS	R24,rec_tail
      D5 9190 0063 LDS	R25,rec_tail+1
      D7 9601      ADIW	R24,1
      D8 9390 0063 STS	rec_tail+1,R25
      DA 9380 0062 STS	rec_tail,R24
(0129) 		//rec_data=RecBuf[rec_tail++]; //you can amend the sentences above two like that
(0130) 		//i++; show that first use it,then add it.
(0131) 		if(rec_tail>=40)	//make up circular queue
      DC 3288      CPI	R24,0x28
      DD E0E0      LDI	R30,0
      DE 079E      CPC	R25,R30
      DF F034      BLT	0x00E6
(0132) 		   rec_tail=0;
      E0 2422      CLR	R2
      E1 2433      CLR	R3
      E2 9230 0063 STS	rec_tail+1,R3
      E4 9220 0062 STS	rec_tail,R2
(0133) 		   
(0134) 		dswin=rec_head<<2;	//the lowest 2 bit of PORTD are RXD and TXD.
      E6 90A0 0060 LDS	R10,rec_head
      E8 90B0 0061 LDS	R11,rec_head+1
      EA 0CAA      LSL	R10
      EB 1CBB      ROL	R11
      EC 0CAA      LSL	R10
      ED 1CBB      ROL	R11
(0135) 	    PORTD=dswin;        //The two ports are occupied,so it need "<<2".
      EE BAA2      OUT	0x12,R10
(0136) 		PORTA=rec_data;     //rec_head++,so it can stand for the number of received data.
      EF 9020 0064 LDS	R2,rec_data
      F1 BA2B      OUT	0x1B,R2
(0137) 		transmit(rec_data);
      F2 2D02      MOV	R16,R2
      F3 DFBC      RCALL	_transmit
(0138) 		if(rec_data==13)	//★??
      F4 9180 0064 LDS	R24,rec_data
      F6 308D      CPI	R24,0xD
      F7 F411      BNE	0x00FA
(0139) 			transmit(10);
FILE: <library>
      F8 E00A      LDI	R16,0xA
      F9 DFB6      RCALL	_transmit
      FA CFC4      RJMP	0x00BF
      FB 9508      RET
push_xgsetF000:
      FC 937A      ST	R23,-Y
      FD 936A      ST	R22,-Y
      FE 935A      ST	R21,-Y
      FF 934A      ST	R20,-Y
     100 9508      RET
pop_xgsetF000:
     101 9149      LD	R20,Y+
     102 9159      LD	R21,Y+
     103 9169      LD	R22,Y+
     104 9179      LD	R23,Y+
     105 9508      RET