{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 5 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register \\fou:n\[1\] register q\[6\]~reg0 52.08 MHz 19.2 ns Internal " "Info: Clock \"clk\" has Internal fmax of 52.08 MHz between source register \"\\fou:n\[1\]\" and destination register \"q\[6\]~reg0\" (period= 19.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.800 ns + Longest register register " "Info: + Longest register to register delay is 17.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\fou:n\[1\] 1 REG LC1_D4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D4; Fanout = 2; REG Node = '\\fou:n\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { \fou:n[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.600 ns) 1.700 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC3_D2 2 " "Info: 2: + IC(1.100 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC3_D2; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { \fou:n[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.800 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC4_D2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 1.800 ns; Loc. = LC4_D2; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.900 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC5_D2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 1.900 ns; Loc. = LC5_D2; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.000 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC6_D2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC6_D2; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.100 ns lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC7_D2 1 " "Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 2.100 ns; Loc. = LC7_D2; Fanout = 1; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.100 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns lpm_add_sub:Add5\|addcore:adder\|unreg_res_node\[6\] 7 COMB LC8_D2 2 " "Info: 7: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC8_D2; Fanout = 2; COMB Node = 'lpm_add_sub:Add5\|addcore:adder\|unreg_res_node\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.400 ns) 5.900 ns Equal1~58 8 COMB LC7_D1 6 " "Info: 8: + IC(1.100 ns) + CELL(1.400 ns) = 5.900 ns; Loc. = LC7_D1; Fanout = 6; COMB Node = 'Equal1~58'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal1~58 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 7.500 ns Equal11~45 9 COMB LC4_D1 11 " "Info: 9: + IC(0.200 ns) + CELL(1.400 ns) = 7.500 ns; Loc. = LC4_D1; Fanout = 11; COMB Node = 'Equal11~45'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { Equal1~58 Equal11~45 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 9.300 ns q~4589 10 COMB LC1_D1 3 " "Info: 10: + IC(0.200 ns) + CELL(1.600 ns) = 9.300 ns; Loc. = LC1_D1; Fanout = 3; COMB Node = 'q~4589'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { Equal11~45 q~4589 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.400 ns) 12.900 ns q~4590 11 COMB LC1_B10 2 " "Info: 11: + IC(2.200 ns) + CELL(1.400 ns) = 12.900 ns; Loc. = LC1_B10; Fanout = 2; COMB Node = 'q~4590'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { q~4589 q~4590 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 15.700 ns q~4625 12 COMB LC8_B4 1 " "Info: 12: + IC(1.200 ns) + CELL(1.600 ns) = 15.700 ns; Loc. = LC8_B4; Fanout = 1; COMB Node = 'q~4625'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { q~4590 q~4625 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.900 ns) 17.800 ns q\[6\]~reg0 13 REG LC1_B6 2 " "Info: 13: + IC(1.200 ns) + CELL(0.900 ns) = 17.800 ns; Loc. = LC1_B6; Fanout = 2; REG Node = 'q\[6\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { q~4625 q[6]~reg0 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.600 ns ( 59.55 % ) " "Info: Total cell delay = 10.600 ns ( 59.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns ( 40.45 % ) " "Info: Total interconnect delay = 7.200 ns ( 40.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.800 ns" { \fou:n[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal1~58 Equal11~45 q~4589 q~4590 q~4625 q[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.800 ns" { \fou:n[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal1~58 Equal11~45 q~4589 q~4590 q~4625 q[6]~reg0 } { 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.100ns 0.200ns 0.200ns 2.200ns 1.200ns 1.200ns } { 0.000ns 0.600ns 0.100ns 0.100ns 0.100ns 0.100ns 1.300ns 1.400ns 1.400ns 1.600ns 1.400ns 1.600ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns q\[6\]~reg0 2 REG LC1_B6 2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_B6; Fanout = 2; REG Node = 'q\[6\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk q[6]~reg0 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk q[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out q[6]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns \\fou:n\[1\] 2 REG LC1_D4 2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_D4; Fanout = 2; REG Node = '\\fou:n\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk \fou:n[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \fou:n[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out \fou:n[1] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk q[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out q[6]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \fou:n[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out \fou:n[1] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.800 ns" { \fou:n[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal1~58 Equal11~45 q~4589 q~4590 q~4625 q[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.800 ns" { \fou:n[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add5|addcore:adder|unreg_res_node[6] Equal1~58 Equal11~45 q~4589 q~4590 q~4625 q[6]~reg0 } { 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.100ns 0.200ns 0.200ns 2.200ns 1.200ns 1.200ns } { 0.000ns 0.600ns 0.100ns 0.100ns 0.100ns 0.100ns 1.300ns 1.400ns 1.400ns 1.600ns 1.400ns 1.600ns 0.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk q[6]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out q[6]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \fou:n[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out \fou:n[1] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] m\[2\] clk 15.400 ns register " "Info: tsu for register \"lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (data pin = \"m\[2\]\", clock pin = \"clk\") is 15.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.200 ns + Longest pin register " "Info: + Longest pin to register delay is 18.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns m\[2\] 1 PIN PIN_41 2 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_41; Fanout = 2; PIN Node = 'm\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[2] } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.500 ns) 8.300 ns Equal0~30 2 COMB LC3_H1 2 " "Info: 2: + IC(3.800 ns) + CELL(1.500 ns) = 8.300 ns; Loc. = LC3_H1; Fanout = 2; COMB Node = 'Equal0~30'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { m[2] Equal0~30 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 10.000 ns lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~183 3 COMB LC6_H1 5 " "Info: 3: + IC(0.200 ns) + CELL(1.500 ns) = 10.000 ns; Loc. = LC6_H1; Fanout = 5; COMB Node = 'lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~183'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { Equal0~30 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~183 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.400 ns) 13.800 ns d\[2\]~128 4 COMB LC2_B8 13 " "Info: 4: + IC(2.400 ns) + CELL(1.400 ns) = 13.800 ns; Loc. = LC2_B8; Fanout = 13; COMB Node = 'd\[2\]~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~183 d[2]~128 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 15.400 ns d\[2\]~133 5 COMB LC1_B8 4 " "Info: 5: + IC(0.200 ns) + CELL(1.400 ns) = 15.400 ns; Loc. = LC1_B8; Fanout = 4; COMB Node = 'd\[2\]~133'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { d[2]~128 d[2]~133 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 17.000 ns d\[2\]~133\$wirecell 6 COMB LC3_B8 6 " "Info: 6: + IC(0.200 ns) + CELL(1.400 ns) = 17.000 ns; Loc. = LC3_B8; Fanout = 6; COMB Node = 'd\[2\]~133\$wirecell'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { d[2]~133 d[2]~133$wirecell } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 18.200 ns lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 7 REG LC6_B8 12 " "Info: 7: + IC(0.200 ns) + CELL(1.000 ns) = 18.200 ns; Loc. = LC6_B8; Fanout = 12; REG Node = 'lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { d[2]~133$wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns ( 61.54 % ) " "Info: Total cell delay = 11.200 ns ( 61.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 38.46 % ) " "Info: Total interconnect delay = 7.000 ns ( 38.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.200 ns" { m[2] Equal0~30 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~183 d[2]~128 d[2]~133 d[2]~133$wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.200 ns" { m[2] m[2]~out Equal0~30 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~183 d[2]~128 d[2]~133 d[2]~133$wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 3.800ns 0.200ns 2.400ns 0.200ns 0.200ns 0.200ns } { 0.000ns 3.000ns 1.500ns 1.500ns 1.400ns 1.400ns 1.400ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數(shù)碼管計數(shù)/bcount/button.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC6_B8 12 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC6_B8; Fanout = 12; REG Node = 'lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.200 ns" { m[2] Equal0~30 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~183 d[2]~128 d[2]~133 d[2]~133$wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.200 ns" { m[2] m[2]~out Equal0~30 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~183 d[2]~128 d[2]~133 d[2]~133$wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 3.800ns 0.200ns 2.400ns 0.200ns 0.200ns 0.200ns } { 0.000ns 3.000ns 1.500ns 1.500ns 1.400ns 1.400ns 1.400ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}