{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[0\] q\[0\]~reg0 10.600 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[0\]\" through register \"q\[0\]~reg0\" is 10.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns q\[0\]~reg0 2 REG LC1_B5 2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_B5; Fanout = 2; REG Node = 'q\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk q[0]~reg0 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk q[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out q[0]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.400 ns + Longest register pin " "Info: + Longest register to pin delay is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[0\]~reg0 1 REG LC1_B5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B5; Fanout = 2; REG Node = 'q\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { q[0]~reg0 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.600 ns) 6.400 ns q\[0\] 2 PIN PIN_150 0 " "Info: 2: + IC(1.800 ns) + CELL(4.600 ns) = 6.400 ns; Loc. = PIN_150; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.400 ns" { q[0]~reg0 q[0] } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 71.88 % ) " "Info: Total cell delay = 4.600 ns ( 71.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 28.13 % ) " "Info: Total interconnect delay = 1.800 ns ( 28.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.400 ns" { q[0]~reg0 q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.400 ns" { q[0]~reg0 q[0] } { 0.000ns 1.800ns } { 0.000ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk q[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out q[0]~reg0 } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.400 ns" { q[0]~reg0 q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.400 ns" { q[0]~reg0 q[0] } { 0.000ns 1.800ns } { 0.000ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:comb_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\] m\[1\] clk -6.100 ns register " "Info: th for register \"lpm_counter:comb_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]\" (data pin = \"m\[1\]\", clock pin = \"clk\") is -6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 50 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 50; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:comb_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\] 2 REG LC8_H2 3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC8_H2; Fanout = 3; REG Node = 'lpm_counter:comb_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns m\[1\] 1 PIN PIN_40 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_40; Fanout = 3; PIN Node = 'm\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m[1] } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.500 ns) 8.300 ns a\[0\]~85 2 COMB LC1_H1 14 " "Info: 2: + IC(3.800 ns) + CELL(1.500 ns) = 8.300 ns; Loc. = LC1_H1; Fanout = 14; COMB Node = 'a\[0\]~85'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { m[1] a[0]~85 } "NODE_NAME" } } { "button.vhd" "" { Text "C:/Documents and Settings/xiaomi/桌面/EDA程序/數碼管計數/bcount/button.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.000 ns) 10.400 ns lpm_counter:comb_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\] 3 REG LC8_H2 3 " "Info: 3: + IC(1.100 ns) + CELL(1.000 ns) = 10.400 ns; Loc. = LC8_H2; Fanout = 3; REG Node = 'lpm_counter:comb_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { a[0]~85 lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 52.88 % ) " "Info: Total cell delay = 5.500 ns ( 52.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 47.12 % ) " "Info: Total interconnect delay = 4.900 ns ( 47.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.400 ns" { m[1] a[0]~85 lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.400 ns" { m[1] m[1]~out a[0]~85 lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 3.800ns 1.100ns } { 0.000ns 3.000ns 1.500ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.400 ns" { m[1] a[0]~85 lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.400 ns" { m[1] m[1]~out a[0]~85 lpm_counter:comb_rtl_2|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 3.800ns 1.100ns } { 0.000ns 3.000ns 1.500ns 1.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 02 13:10:27 2009 " "Info: Processing ended: Thu Apr 02 13:10:27 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}