INCLUDE REG_51.PDF

;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
;		PORT DECLERATION
;%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

FRONT	EQU	P1.6
BACK 	EQU	P1.7
LEFT	EQU	P1.3
RIGHT	EQU	P1.5

CSEG     AT      0        ; RESET VECTOR
;---------==========----------==========---------=========---------
;              PROCESSOR INTERRUPT AND RESET VECTORS
;---------==========----------==========---------=========---------
 
		ORG 00H    		; Reset
		MOV SP,#60H
		MOV P1,#0FFH
		MOV TMOD,#20H
		MOV TH1,#0FDH
		MOV SCON,#50H
		SETB TR1
		
		
MAIN:		
		JNB RI,$
		MOV A,SBUF
		CJNE A,#'8',DFG1			;FRONT
		CLR FRONT
		SETB LEFT
		SETB RIGHT
		SETB BACK
		AJMP DOWN
DFG1:	CJNE A,#'2',DFG2			;BACK
		CLR BACK
		SETB LEFT1
		SETB RIGHT
		SETB FRONT
		AJMP DOWN
DFG2:	CJNE A,#'4',DFG3			;LEFT
		CLR LEFT
		SETB BACK
		SETB RIGHT
		SETB FRONT
		AJMP DOWN
DFG3:	CJNE A,#'6',DFG4			;RIGHT
		CLR RIGHT
		SETB LEFT
		SETB BACK
		SETB FRONT
		AJMP DOWN
DFG4:	CJNE A,#'9',DFG5			;FRONT + RIGHT
		CLR RIGHT
		CLR FRONT
		SETB LEFT
		SETB BACK		 
		AJMP DOWN
DFG5:	CJNE A,#'7',DFG6			;FRONT + LEFT
		CLR LEFT
		CLR FRONT
		SETB RIGHT
		SETB BACK		 
		AJMP DOWN
DFG6:	CJNE A,#'3',DFG7			;BACK + RIGHT
		CLR RIGHT
		CLR BACK
		SETB LEFT
		SETB FRONT		 
		AJMP DOWN
DFG7:	CJNE A,#'1',DFG8			;BACK + LEFT
		SETB RIGHT
		SETB FRONT
		CLR LEFT
		CLR BACK		 
		AJMP DOWN
DFG8:	CJNE A,#'5',DOWN			;STOP
		SETB RIGHT
		SETB FRONT
		SETB LEFT
		SETB BACK		 
		AJMP DOWN
DOWN:	CLR RI
		AJMP MAIN
;**********************************************************
  END