#define Q_TYPE_ITD	__constant_cpu_to_le32 (0 << 1)#define Q_TYPE_QH	__constant_cpu_to_le32 (1 << 1)#define Q_TYPE_SITD	__constant_cpu_to_le32 (2 << 1)#define Q_TYPE_FSTN	__constant_cpu_to_le32 (3 << 1)/* next async queue entry, or pointer to interrupt/periodic QH */#define	QH_NEXT(dma)	(cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)/* for periodic/async schedules and qtd lists, mark end of list */#define	EHCI_LIST_END	__constant_cpu_to_le32(1) /* "null pointer" to hw *//* * Entries in periodic shadow table are pointers to one of four kinds * of data structure.  That's dictated by the hardware; a type tag is * encoded in the low bits of the hardware's periodic schedule.  Use * Q_NEXT_TYPE to get the tag. * * For entries in the async schedule, the type tag always says "qh". */union ehci_shadow {	struct ehci_qh		*qh;		/* Q_TYPE_QH */	struct ehci_itd		*itd;		/* Q_TYPE_ITD */	struct ehci_sitd	*sitd;		/* Q_TYPE_SITD */	struct ehci_fstn	*fstn;		/* Q_TYPE_FSTN */	__le32			*hw_next;	/* (all types) */	void			*ptr;};/*-------------------------------------------------------------------------*//* * EHCI Specification 0.95 Section 3.6 * QH: describes control/bulk/interrupt endpoints * See Fig 3-7 "Queue Head Structure Layout". * * These appear in both the async and (for interrupt) periodic schedules. */struct ehci_qh {	/* first part defined by EHCI spec */	__le32			hw_next;	 /* see EHCI 3.6.1 */	__le32			hw_info1;        /* see EHCI 3.6.2 */#define	QH_HEAD		0x00008000	__le32			hw_info2;        /* see EHCI 3.6.2 */#define	QH_SMASK	0x000000ff#define	QH_CMASK	0x0000ff00#define	QH_HUBADDR	0x007f0000#define	QH_HUBPORT	0x3f800000#define	QH_MULT		0xc0000000	__le32			hw_current;	 /* qtd list - see EHCI 3.6.4 */	/* qtd overlay (hardware parts of a struct ehci_qtd) */	__le32			hw_qtd_next;	__le32			hw_alt_next;	__le32			hw_token;	__le32			hw_buf [5];	__le32			hw_buf_hi [5];	/* the rest is HCD-private */	dma_addr_t		qh_dma;		/* address of qh */	union ehci_shadow	qh_next;	/* ptr to qh; or periodic */	struct list_head	qtd_list;	/* sw qtd list */	struct ehci_qtd		*dummy;	struct ehci_qh		*reclaim;	/* next to reclaim */	struct ehci_hcd		*ehci;	struct kref		kref;	unsigned		stamp;	u8			qh_state;#define	QH_STATE_LINKED		1		/* HC sees this */#define	QH_STATE_UNLINK		2		/* HC may still see this */#define	QH_STATE_IDLE		3		/* HC doesn't see this */#define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on reclaim q */#define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */	/* periodic schedule info */	u8			usecs;		/* intr bandwidth */	u8			gap_uf;		/* uframes split/csplit gap */	u8			c_usecs;	/* ... split completion bw */	u16			tt_usecs;	/* tt downstream bandwidth */	unsigned short		period;		/* polling interval */	unsigned short		start;		/* where polling starts */#define NO_FRAME ((unsigned short)~0)			/* pick new start */	struct usb_device	*dev;		/* access to TT */} __attribute__ ((aligned (32)));/*-------------------------------------------------------------------------*//* description of one iso transaction (up to 3 KB data if highspeed) */struct ehci_iso_packet {	/* These will be copied to iTD when scheduling */	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */	__le32			transaction;	/* itd->hw_transaction[i] |= */	u8			cross;		/* buf crosses pages */	/* for full speed OUT splits */	u32			buf1;};/* temporary schedule data for packets from iso urbs (both speeds) * each packet is one logical usb transaction to the device (not TT), * beginning at stream->next_uframe */struct ehci_iso_sched {	struct list_head	td_list;	unsigned		span;	struct ehci_iso_packet	packet [0];};/* * ehci_iso_stream - groups all (s)itds for this endpoint. * acts like a qh would, if EHCI had them for ISO. */struct ehci_iso_stream {	/* first two fields match QH, but info1 == 0 */	__le32			hw_next;	__le32			hw_info1;	u32			refcount;	u8			bEndpointAddress;	u8			highspeed;	u16			depth;		/* depth in uframes */	struct list_head	td_list;	/* queued itds/sitds */	struct list_head	free_list;	/* list of unused itds/sitds */	struct usb_device	*udev;	struct usb_host_endpoint *ep;	/* output of (re)scheduling */	unsigned long		start;		/* jiffies */	unsigned long		rescheduled;	int			next_uframe;	__le32			splits;	/* the rest is derived from the endpoint descriptor,	 * trusting urb->interval == f(epdesc->bInterval) and	 * including the extra info for hw_bufp[0..2]	 */	u8			interval;	u8			usecs, c_usecs;	u16			tt_usecs;	u16			maxp;	u16			raw_mask;	unsigned		bandwidth;	/* This is used to initialize iTD's hw_bufp fields */	__le32			buf0;	__le32			buf1;	__le32			buf2;	/* this is used to initialize sITD's tt info */	__le32			address;};/*-------------------------------------------------------------------------*//* * EHCI Specification 0.95 Section 3.3 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" * * Schedule records for high speed iso xfers */struct ehci_itd {	/* first part defined by EHCI spec */	__le32			hw_next;           /* see EHCI 3.3.1 */	__le32			hw_transaction [8]; /* see EHCI 3.3.2 */#define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */#define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */#define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */#define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */#define	EHCI_ITD_LENGTH(tok)	(((tok)>>16) & 0x0fff)#define	EHCI_ITD_IOC		(1 << 15)	/* interrupt on complete */#define ITD_ACTIVE	__constant_cpu_to_le32(EHCI_ISOC_ACTIVE)	__le32			hw_bufp [7];	/* see EHCI 3.3.3 */	__le32			hw_bufp_hi [7];	/* Appendix B */	/* the rest is HCD-private */	dma_addr_t		itd_dma;	/* for this itd */	union ehci_shadow	itd_next;	/* ptr to periodic q entry */	struct urb		*urb;	struct ehci_iso_stream	*stream;	/* endpoint's queue */	struct list_head	itd_list;	/* list of stream's itds */	/* any/all hw_transactions here may be used by that urb */	unsigned		frame;		/* where scheduled */	unsigned		pg;	unsigned		index[8];	/* in urb->iso_frame_desc */	u8			usecs[8];} __attribute__ ((aligned (32)));/*-------------------------------------------------------------------------*//* * EHCI Specification 0.95 Section 3.4 * siTD, aka split-transaction isochronous Transfer Descriptor *       ... describe full speed iso xfers through TT in hubs * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) */struct ehci_sitd {	/* first part defined by EHCI spec */	__le32			hw_next;/* uses bit field macros above - see EHCI 0.95 Table 3-8 */	__le32			hw_fullspeed_ep;	/* EHCI table 3-9 */	__le32			hw_uframe;		/* EHCI table 3-10 */	__le32			hw_results;		/* EHCI table 3-11 */#define	SITD_IOC	(1 << 31)	/* interrupt on completion */#define	SITD_PAGE	(1 << 30)	/* buffer 0/1 */#define	SITD_LENGTH(x)	(0x3ff & ((x)>>16))#define	SITD_STS_ACTIVE	(1 << 7)	/* HC may execute this */#define	SITD_STS_ERR	(1 << 6)	/* error from TT */#define	SITD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */#define	SITD_STS_BABBLE	(1 << 4)	/* device was babbling */#define	SITD_STS_XACT	(1 << 3)	/* illegal IN response */#define	SITD_STS_MMF	(1 << 2)	/* incomplete split transaction */#define	SITD_STS_STS	(1 << 1)	/* split transaction state */#define SITD_ACTIVE	__constant_cpu_to_le32(SITD_STS_ACTIVE)	__le32			hw_buf [2];		/* EHCI table 3-12 */	__le32			hw_backpointer;		/* EHCI table 3-13 */	__le32			hw_buf_hi [2];		/* Appendix B */	/* the rest is HCD-private */	dma_addr_t		sitd_dma;	union ehci_shadow	sitd_next;	/* ptr to periodic q entry */	struct urb		*urb;	struct ehci_iso_stream	*stream;	/* endpoint's queue */	struct list_head	sitd_list;	/* list of stream's sitds */	unsigned		frame;	unsigned		index;} __attribute__ ((aligned (32)));/*-------------------------------------------------------------------------*//* * EHCI Specification 0.96 Section 3.7 * Periodic Frame Span Traversal Node (FSTN) * * Manages split interrupt transactions (using TT) that span frame boundaries * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN * makes the HC jump (back) to a QH to scan for fs/ls QH completions until * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. */struct ehci_fstn {	__le32			hw_next;	/* any periodic q entry */	__le32			hw_prev;	/* qh or EHCI_LIST_END */	/* the rest is HCD-private */	dma_addr_t		fstn_dma;	union ehci_shadow	fstn_next;	/* ptr to periodic q entry */} __attribute__ ((aligned (32)));/*-------------------------------------------------------------------------*/#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT/* * Some EHCI controllers have a Transaction Translator built into the * root hub. This is a non-standard feature.  Each controller will need * to add code to the following inline functions, and call them as * needed (mostly in root hub code). */#define	ehci_is_TDI(e)			((e)->is_tdi_rh_tt)/* Returns the speed of a device attached to a port on the root hub. */static inline unsigned intehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc){	if (ehci_is_TDI(ehci)) {		switch ((portsc>>26)&3) {		case 0:			return 0;		case 1:			return (1<<USB_PORT_FEAT_LOWSPEED);		case 2:		default:			return (1<<USB_PORT_FEAT_HIGHSPEED);		}	}	return (1<<USB_PORT_FEAT_HIGHSPEED);}#else#define	ehci_is_TDI(e)			(0)#define	ehci_port_speed(ehci, portsc)	(1<<USB_PORT_FEAT_HIGHSPEED)#endif/*-------------------------------------------------------------------------*/#ifdef CONFIG_PPC_83xx/* Some Freescale processors have an erratum in which the TT * port number in the queue head was 0..N-1 instead of 1..N. */#define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)#else#define	ehci_has_fsl_portno_bug(e)		(0)#endif/* * While most USB host controllers implement their registers in * little-endian format, a minority (celleb companion chip) implement * them in big endian format. * * This attempts to support either format at compile time without a * runtime penalty, or both formats with the additional overhead * of checking a flag bit. */#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO#define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)#else#define ehci_big_endian_mmio(e)		0#endifstatic inline unsigned int ehci_readl (const struct ehci_hcd *ehci,				       __u32 __iomem * regs){#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO	return ehci_big_endian_mmio(ehci) ?		readl_be(regs) :		readl(regs);#else	return readl(regs);#endif}static inline void ehci_writel (const struct ehci_hcd *ehci,				const unsigned int val, __u32 __iomem *regs){#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO	ehci_big_endian_mmio(ehci) ?		writel_be(val, regs) :		writel(val, regs);#else	writel(val, regs);#endif}/*-------------------------------------------------------------------------*/#ifndef DEBUG#define STUB_DEBUG_FILES#endif	/* DEBUG *//*-------------------------------------------------------------------------*/#endif /* __LINUX_EHCI_HCD_H */