/* ========================================================================== * * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless * otherwise expressly agreed to in writing between Synopsys and you. * * The Software IS NOT an item of Licensed Software or Licensed Product under * any End User Software License Agreement or Agreement for Licensed Product * with Synopsys or any supplement thereto. You are permitted to use and * redistribute this Software in source and binary forms, with or without * modification, provided that redistributions of source code must retain this * notice. You may not view, use, disclose, copy or distribute this file or * any information contained herein except pursuant to this license grant from * Synopsys. If you do not agree with this notice, including the disclaimer * below, then you are not authorized to use the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * DAMAGE. * ========================================================================== */#ifndef __DWC_OTG_REGS_H__#define __DWC_OTG_REGS_H__/** * @file * * This file contains the data structures for accessing the DWC_otg core registers. * * The application interfaces with the HS OTG core by reading from and * writing to the Control and Status Register (CSR) space through the * AHB Slave interface. These registers are 32 bits wide, and the * addresses are 32-bit-block aligned. * CSRs are classified as follows: * - Core Global Registers * - Device Mode Registers * - Device Global Registers * - Device Endpoint Specific Registers * - Host Mode Registers * - Host Global Registers * - Host Port CSRs * - Host Channel Specific Registers * * Only the Core Global registers can be accessed in both Device and * Host modes. When the HS OTG core is operating in one mode, either * Device or Host, the application must not access registers from the * other mode. When the core switches from one mode to another, the * registers in the new mode of operation must be reprogrammed as they * would be after a power-on reset. *//****************************************************************************//** DWC_otg Core registers . * The dwc_otg_core_global_regs structure defines the size * and relative field offsets for the Core Global registers. */typedef struct dwc_otg_core_global_regs {	/** OTG Control and Status Register.	<i>Offset: 000h</i> */	volatile uint32_t gotgctl;	/** OTG Interrupt Register.		<i>Offset: 004h</i> */	volatile uint32_t gotgint;	/**Core AHB Configuration Register.	<i>Offset: 008h</i> */	volatile uint32_t gahbcfg;#define DWC_GLBINTRMASK		0x0001#define DWC_DMAENABLE		0x0020#define DWC_NPTXEMPTYLVL_EMPTY	0x0080#define DWC_NPTXEMPTYLVL_HALFEMPTY	0x0000#define DWC_PTXEMPTYLVL_EMPTY	0x0100#define DWC_PTXEMPTYLVL_HALFEMPTY	0x0000	/**Core USB Configuration Register.	 <i>Offset: 00Ch</i> */	volatile uint32_t gusbcfg;	/**Core Reset Register.	 <i>Offset: 010h</i> */	volatile uint32_t grstctl;	/**Core Interrupt Register.	 <i>Offset: 014h</i> */	volatile uint32_t gintsts;	/**Core Interrupt Mask Register.  <i>Offset: 018h</i> */	volatile uint32_t gintmsk;	/**Receive Status Queue Read Register (Read Only).	<i>Offset: 01Ch</i> */	volatile uint32_t grxstsr;	/**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/	volatile uint32_t grxstsp;	/**Receive FIFO Size Register.	<i>Offset: 024h</i> */	volatile uint32_t grxfsiz;	/**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */	volatile uint32_t gnptxfsiz;	/**Non Periodic Transmit FIFO/Queue Status Register (Read	 * Only). <i>Offset: 02Ch</i> */	volatile uint32_t gnptxsts;	/**I2C Access Register.	 <i>Offset: 030h</i> */	volatile uint32_t gi2cctl;	/**PHY Vendor Control Register.	 <i>Offset: 034h</i> */	volatile uint32_t gpvndctl;	/**General Purpose Input/Output Register.  <i>Offset: 038h</i> */	volatile uint32_t ggpio;	/**User ID Register.  <i>Offset: 03Ch</i> */	volatile uint32_t guid;	/**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */	volatile uint32_t gsnpsid;	/**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */	volatile uint32_t ghwcfg1;	/**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */	volatile uint32_t ghwcfg2;#define DWC_SLAVE_ONLY_ARCH	0#define DWC_EXT_DMA_ARCH	1#define DWC_INT_DMA_ARCH	2#define DWC_MODE_HNP_SRP_CAPABLE	0#define DWC_MODE_SRP_ONLY_CAPABLE	1#define DWC_MODE_NO_HNP_SRP_CAPABLE	2#define DWC_MODE_SRP_CAPABLE_DEVICE	3#define DWC_MODE_NO_SRP_CAPABLE_DEVICE	4#define DWC_MODE_SRP_CAPABLE_HOST	5#define DWC_MODE_NO_SRP_CAPABLE_HOST	6	/**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */	volatile uint32_t ghwcfg3;	/**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/	volatile uint32_t ghwcfg4;	/** Reserved  <i>Offset: 054h-0FFh</i> */	volatile uint32_t reserved[43];	/** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */	volatile uint32_t hptxfsiz;	/** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,		otherwise Device Transmit FIFO#n Register.	 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */	volatile uint32_t dptxfsiz_dieptxf[15];} dwc_otg_core_global_regs_t;/** * This union represents the bit fields of the Core OTG Control * and Status Register (GOTGCTL).  Set the bits using the bit * fields then write the <i>d32</i> value to the register. */typedef union gotgctl_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		unsigned sesreqscs:1;		unsigned sesreq:1;		unsigned reserved2_7:6;		unsigned hstnegscs:1;		unsigned hnpreq:1;		unsigned hstsethnpen:1;		unsigned devhnpen:1;		unsigned reserved12_15:4;		unsigned conidsts:1;		unsigned reserved17:1;		unsigned asesvld:1;		unsigned bsesvld:1;		unsigned currmod:1;		unsigned reserved21_31:11;	} b;} gotgctl_data_t;/** * This union represents the bit fields of the Core OTG Interrupt Register * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i> * value to the register. */typedef union gotgint_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		/** Current Mode */		unsigned reserved0_1:2;		/** Session End Detected */		unsigned sesenddet:1;		unsigned reserved3_7:5;		/** Session Request Success Status Change */		unsigned sesreqsucstschng:1;		/** Host Negotiation Success Status Change */		unsigned hstnegsucstschng:1;		unsigned reserver10_16:7;		/** Host Negotiation Detected */		unsigned hstnegdet:1;		/** A-Device Timeout Change */		unsigned adevtoutchng:1;		/** Debounce Done */		unsigned debdone:1;		unsigned reserved31_20:12;	} b;} gotgint_data_t;/** * This union represents the bit fields of the Core AHB Configuration * Register (GAHBCFG).	Set/clear the bits using the bit fields then * write the <i>d32</i> value to the register. */typedef union gahbcfg_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		unsigned glblintrmsk:1;#define DWC_GAHBCFG_GLBINT_ENABLE		1		unsigned hburstlen:4;#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE	0#define DWC_GAHBCFG_INT_DMA_BURST_INCR		1#define DWC_GAHBCFG_INT_DMA_BURST_INCR4		3#define DWC_GAHBCFG_INT_DMA_BURST_INCR8		5#define DWC_GAHBCFG_INT_DMA_BURST_INCR16	7		unsigned dmaenable:1;#define DWC_GAHBCFG_DMAENABLE			1		unsigned reserved:1;		unsigned nptxfemplvl_txfemplvl:1;		unsigned ptxfemplvl:1;#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY		1#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY	0		unsigned reserved9_31:23;	} b;} gahbcfg_data_t;/** * This union represents the bit fields of the Core USB Configuration * Register (GUSBCFG).	Set the bits using the bit fields then write * the <i>d32</i> value to the register. */typedef union gusbcfg_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		unsigned toutcal:3;		unsigned phyif:1;		unsigned ulpi_utmi_sel:1;		unsigned fsintf:1;		unsigned physel:1;		unsigned ddrsel:1;		unsigned srpcap:1;		unsigned hnpcap:1;		unsigned usbtrdtim:4;		unsigned nptxfrwnden:1;		unsigned phylpwrclksel:1;		unsigned otgutmifssel:1;		unsigned ulpi_fsls:1;		unsigned ulpi_auto_res:1;		unsigned ulpi_clk_sus_m:1;		unsigned ulpi_ext_vbus_drv:1;		unsigned ulpi_int_vbus_indicator:1;		unsigned term_sel_dl_pulse:1;		unsigned reserved:9;	} b;} gusbcfg_data_t;/** * This union represents the bit fields of the Core Reset Register * (GRSTCTL).  Set/clear the bits using the bit fields then write the * <i>d32</i> value to the register. */typedef union grstctl_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		/** Core Soft Reset (CSftRst) (Device and Host)		 *		 * The application can flush the control logic in the		 * entire core using this bit. This bit resets the		 * pipelines in the AHB Clock domain as well as the		 * PHY Clock domain.		 *		 * The state machines are reset to an IDLE state, the		 * control bits in the CSRs are cleared, all the		 * transmit FIFOs and the receive FIFO are flushed.		 *		 * The status mask bits that control the generation of		 * the interrupt, are cleared, to clear the		 * interrupt. The interrupt status bits are not		 * cleared, so the application can get the status of		 * any events that occurred in the core after it has		 * set this bit.		 *		 * Any transactions on the AHB are terminated as soon		 * as possible following the protocol. Any		 * transactions on the USB are terminated immediately.		 *		 * The configuration settings in the CSRs are		 * unchanged, so the software doesn't have to		 * reprogram these registers (Device		 * Configuration/Host Configuration/Core System		 * Configuration/Core PHY Configuration).		 *		 * The application can write to this bit, any time it		 * wants to reset the core. This is a self clearing		 * bit and the core clears this bit after all the		 * necessary logic is reset in the core, which may		 * take several clocks, depending on the current state		 * of the core.		 */		unsigned csftrst:1;		/** Hclk Soft Reset		 *		 * The application uses this bit to reset the control logic in		 * the AHB clock domain. Only AHB clock domain pipelines are		 * reset.		 */		unsigned hsftrst:1;		/** Host Frame Counter Reset (Host Only)<br>		 *		 * The application can reset the (micro)frame number		 * counter inside the core, using this bit. When the		 * (micro)frame counter is reset, the subsequent SOF		 * sent out by the core, will have a (micro)frame		 * number of 0.		 */		unsigned hstfrm:1;		/** In Token Sequence Learning Queue Flush		 * (INTknQFlsh) (Device Only)		 */		unsigned intknqflsh:1;		/** RxFIFO Flush (RxFFlsh) (Device and Host)		 *		 * The application can flush the entire Receive FIFO		 * using this bit.	<p>The application must first		 * ensure that the core is not in the middle of a		 * transaction.	 <p>The application should write into		 * this bit, only after making sure that neither the		 * DMA engine is reading from the RxFIFO nor the MAC		 * is writing the data in to the FIFO.	<p>The		 * application should wait until the bit is cleared		 * before performing any other operations. This bit		 * will takes 8 clocks (slowest of PHY or AHB clock)		 * to clear.		 */		unsigned rxfflsh:1;		/** TxFIFO Flush (TxFFlsh) (Device and Host).		 *		 * This bit is used to selectively flush a single or		 * all transmit FIFOs.	The application must first		 * ensure that the core is not in the middle of a		 * transaction.	 <p>The application should write into		 * this bit, only after making sure that neither the		 * DMA engine is writing into the TxFIFO nor the MAC		 * is reading the data out of the FIFO.	 <p>The		 * application should wait until the core clears this		 * bit, before performing any operations. This bit		 * will takes 8 clocks (slowest of PHY or AHB clock)		 * to clear.		 */		unsigned txfflsh:1;		/** TxFIFO Number (TxFNum) (Device and Host).		 *		 * This is the FIFO number which needs to be flushed,		 * using the TxFIFO Flush bit. This field should not		 * be changed until the TxFIFO Flush bit is cleared by		 * the core.		 *	 - 0x0 : Non Periodic TxFIFO Flush		 *	 - 0x1 : Periodic TxFIFO #1 Flush in device mode		 *	   or Periodic TxFIFO in host mode		 *	 - 0x2 : Periodic TxFIFO #2 Flush in device mode.		 *	 - ...		 *	 - 0xF : Periodic TxFIFO #15 Flush in device mode		 *	 - 0x10: Flush all the Transmit NonPeriodic and		 *	   Transmit Periodic FIFOs in the core		 */		unsigned txfnum:5;		/** Reserved */		unsigned reserved11_29:19;		/** DMA Request Signal.	 Indicated DMA request is in		 * probress.  Used for debug purpose. */		unsigned dmareq:1;		/** AHB Master Idle.  Indicates the AHB Master State		 * Machine is in IDLE condition. */		unsigned ahbidle:1;	} b;} grstctl_t;/** * This union represents the bit fields of the Core Interrupt Mask * Register (GINTMSK).	Set/clear the bits using the bit fields then * write the <i>d32</i> value to the register. */typedef union gintmsk_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		unsigned reserved0:1;		unsigned modemismatch:1;		unsigned otgintr:1;		unsigned sofintr:1;		unsigned rxstsqlvl:1;		unsigned nptxfempty:1;		unsigned ginnakeff:1;		unsigned goutnakeff:1;		unsigned reserved8:1;		unsigned i2cintr:1;		unsigned erlysuspend:1;		unsigned usbsuspend:1;		unsigned usbreset:1;		unsigned enumdone:1;		unsigned isooutdrop:1;		unsigned eopframe:1;		unsigned reserved16:1;		unsigned epmismatch:1;		unsigned inepintr:1;		unsigned outepintr:1;		unsigned incomplisoin:1;		unsigned incomplisoout:1;		unsigned reserved22_23:2;		unsigned portintr:1;		unsigned hcintr:1;		unsigned ptxfempty:1;		unsigned reserved27:1;		unsigned conidstschng:1;		unsigned disconnect:1;		unsigned sessreqintr:1;		unsigned wkupintr:1;	} b;} gintmsk_data_t;/** * This union represents the bit fields of the Core Interrupt Register * (GINTSTS).  Set/clear the bits using the bit fields then write the * <i>d32</i> value to the register. */typedef union gintsts_data {	/** raw register data */	uint32_t d32;#define DWC_SOF_INTR_MASK 0x0008	/** register bits */	struct {#define DWC_HOST_MODE 1		unsigned curmode:1;		unsigned modemismatch:1;		unsigned otgintr:1;		unsigned sofintr:1;		unsigned rxstsqlvl:1;		unsigned nptxfempty:1;		unsigned ginnakeff:1;		unsigned goutnakeff:1;		unsigned reserved8:1;		unsigned i2cintr:1;		unsigned erlysuspend:1;		unsigned usbsuspend:1;		unsigned usbreset:1;		unsigned enumdone:1;		unsigned isooutdrop:1;		unsigned eopframe:1;		unsigned intokenrx:1;		unsigned epmismatch:1;		unsigned inepint:1;		unsigned outepintr:1;		unsigned incomplisoin:1;		unsigned incomplisoout:1;		unsigned reserved22_23:2;		unsigned portintr:1;		unsigned hcintr:1;		unsigned ptxfempty:1;		unsigned reserved27:1;		unsigned conidstschng:1;		unsigned disconnect:1;		unsigned sessreqintr:1;		unsigned wkupintr:1;	} b;} gintsts_data_t;/** * This union represents the bit fields in the Device Receive Status Read and * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> * element then read out the bits using the <i>b</i>it elements. */typedef union device_grxsts_data {	/** raw register data */	uint32_t d32;	/** register bits */	struct {		unsigned epnum:4;		unsigned bcnt:11;		unsigned dpid:2;