/* ========================================================================== * * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless * otherwise expressly agreed to in writing between Synopsys and you. * * The Software IS NOT an item of Licensed Software or Licensed Product under * any End User Software License Agreement or Agreement for Licensed Product * with Synopsys or any supplement thereto. You are permitted to use and * redistribute this Software in source and binary forms, with or without * modification, provided that redistributions of source code must retain this * notice. You may not view, use, disclose, copy or distribute this file or * any information contained herein except pursuant to this license grant from * Synopsys. If you do not agree with this notice, including the disclaimer * below, then you are not authorized to use the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * DAMAGE. * ========================================================================== */#if !defined(__DWC_CIL_H__)#define __DWC_CIL_H__#include "dwc_otg_plat.h"#include "dwc_otg_regs.h"#ifdef DEBUG#include "linux/timer.h"#endif/** * @file * This file contains the interface to the Core Interface Layer. *//** * The <code>dwc_ep</code> structure represents the state of a single * endpoint when acting in device mode. It contains the data items * needed for an endpoint to be activated and transfer packets. */typedef struct dwc_ep{	/** EP number used for register address lookup */	uint8_t	 num;	/** EP direction 0 = OUT */	unsigned is_in : 1;	/** EP active. */	unsigned active : 1;	/** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO		If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/	unsigned tx_fifo_num : 4;	/** EP type: 0 - Control, 1 - ISOC,	 2 - BULK,	3 - INTR */	unsigned type : 2;#define DWC_OTG_EP_TYPE_CONTROL	   0#define DWC_OTG_EP_TYPE_ISOC	   1#define DWC_OTG_EP_TYPE_BULK	   2#define DWC_OTG_EP_TYPE_INTR	   3	/** DATA start PID for INTR and BULK EP */	unsigned data_pid_start : 1;	/** Frame (even/odd) for ISOC EP */	unsigned even_odd_frame : 1;	/** Max Packet bytes */	unsigned maxpacket : 11;	/** @name Transfer state */	/** @{ */	/**	 * Pointer to the beginning of the transfer buffer -- do not modify	 * during transfer.	 */	uint32_t dma_addr;	uint32_t dma_desc_addr;	dwc_otg_dma_desc_t* desc_addr;	uint8_t *start_xfer_buff;	/** pointer to the transfer buffer */	uint8_t *xfer_buff;	/** Number of bytes to transfer */	unsigned xfer_len : 19;	/** Number of bytes transferred. */	unsigned xfer_count : 19;	/** Sent ZLP */	unsigned sent_zlp : 1;	/** Total len for control transfer */	unsigned total_len : 19;	/** stall clear flag */	unsigned stall_clear_flag : 1;#ifdef _EN_ISOC_	/**	 * Variables specific for ISOC EPs	 *	 */	/** DMA addresses of ISOC buffers */	uint32_t dma_addr0;	uint32_t dma_addr1;	uint32_t iso_dma_desc_addr;	dwc_otg_iso_dma_desc_t* iso_desc_addr;	/** pointer to the transfer buffers */	uint8_t *xfer_buff0;	uint8_t *xfer_buff1;	/** number of ISOC Buffer is processing */	uint32_t proc_buf_num;	/** Interval of ISOC Buffer processing */	uint32_t buf_proc_intrvl;	/** Data size for regular frame */	uint32_t data_per_frame;	/* todo - pattern data support is to be implemented in the future */	/** Data size for pattern frame */	uint32_t data_pattern_frame;	/** Frame number of pattern data */	uint32_t sync_frame;	/** bInterval */	uint32_t bInterval;	/** DMA Desc count for buffers */	uint32_t desc_cnt;	/** ISO Packet number per frame */	uint32_t pkt_per_frm;	/** Next frame num for which will be setup DMA Desc */	uint32_t next_frame;#endif //_EN_ISOC_/** @} */} dwc_ep_t;/* * Reasons for halting a host channel. */typedef enum dwc_otg_halt_status{	DWC_OTG_HC_XFER_NO_HALT_STATUS,	DWC_OTG_HC_XFER_COMPLETE,	DWC_OTG_HC_XFER_URB_COMPLETE,	DWC_OTG_HC_XFER_ACK,	DWC_OTG_HC_XFER_NAK,	DWC_OTG_HC_XFER_NYET,	DWC_OTG_HC_XFER_STALL,	DWC_OTG_HC_XFER_XACT_ERR,	DWC_OTG_HC_XFER_FRAME_OVERRUN,	DWC_OTG_HC_XFER_BABBLE_ERR,	DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,	DWC_OTG_HC_XFER_AHB_ERR,	DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,	DWC_OTG_HC_XFER_URB_DEQUEUE} dwc_otg_halt_status_e;/** * Host channel descriptor. This structure represents the state of a single * host channel when acting in host mode. It contains the data items needed to * transfer packets to an endpoint via a host channel. */typedef struct dwc_hc{	/** Host channel number used for register address lookup */	uint8_t	 hc_num;	/** Device to access */	unsigned dev_addr : 7;	/** EP to access */	unsigned ep_num : 4;	/** EP direction. 0: OUT, 1: IN */	unsigned ep_is_in : 1;	/**	 * EP speed.	 * One of the following values:	 *	- DWC_OTG_EP_SPEED_LOW	 *	- DWC_OTG_EP_SPEED_FULL	 *	- DWC_OTG_EP_SPEED_HIGH	 */	unsigned speed : 2;#define DWC_OTG_EP_SPEED_LOW	0#define DWC_OTG_EP_SPEED_FULL	1#define DWC_OTG_EP_SPEED_HIGH	2	/**	 * Endpoint type.	 * One of the following values:	 *	- DWC_OTG_EP_TYPE_CONTROL: 0	 *	- DWC_OTG_EP_TYPE_ISOC: 1	 *	- DWC_OTG_EP_TYPE_BULK: 2	 *	- DWC_OTG_EP_TYPE_INTR: 3	 */	unsigned ep_type : 2;	/** Max packet size in bytes */	unsigned max_packet : 11;	/**	 * PID for initial transaction.	 * 0: DATA0,<br>	 * 1: DATA2,<br>	 * 2: DATA1,<br>	 * 3: MDATA (non-Control EP),	 *	  SETUP (Control EP)	 */	unsigned data_pid_start : 2;#define DWC_OTG_HC_PID_DATA0 0#define DWC_OTG_HC_PID_DATA2 1#define DWC_OTG_HC_PID_DATA1 2#define DWC_OTG_HC_PID_MDATA 3#define DWC_OTG_HC_PID_SETUP 3	/** Number of periodic transactions per (micro)frame */	unsigned multi_count: 2;	/** @name Transfer State */	/** @{ */	/** Pointer to the current transfer buffer position. */	uint8_t *xfer_buff;	/** Total number of bytes to transfer. */	uint32_t xfer_len;	/** Number of bytes transferred so far. */	uint32_t xfer_count;	/** Packet count at start of transfer.*/	uint16_t start_pkt_count;	/**	 * Flag to indicate whether the transfer has been started. Set to 1 if	 * it has been started, 0 otherwise.	 */	uint8_t xfer_started;	/**	 * Set to 1 to indicate that a PING request should be issued on this	 * channel. If 0, process normally.	 */	uint8_t do_ping;	/**	 * Set to 1 to indicate that the error count for this transaction is	 * non-zero. Set to 0 if the error count is 0.	 */	uint8_t error_state;	/**	 * Set to 1 to indicate that this channel should be halted the next	 * time a request is queued for the channel. This is necessary in	 * slave mode if no request queue space is available when an attempt	 * is made to halt the channel.	 */	uint8_t halt_on_queue;	/**	 * Set to 1 if the host channel has been halted, but the core is not	 * finished flushing queued requests. Otherwise 0.	 */	uint8_t halt_pending;	/**	 * Reason for halting the host channel.	 */	dwc_otg_halt_status_e	halt_status;	/*	 * Split settings for the host channel	 */	uint8_t do_split;		   /**< Enable split for the channel */	uint8_t complete_split;	   /**< Enable complete split */	uint8_t hub_addr;		   /**< Address of high speed hub */	uint8_t port_addr;		   /**< Port of the low/full speed device */	/** Split transaction position	 * One of the following values:	 *	  - DWC_HCSPLIT_XACTPOS_MID	 *	  - DWC_HCSPLIT_XACTPOS_BEGIN	 *	  - DWC_HCSPLIT_XACTPOS_END	 *	  - DWC_HCSPLIT_XACTPOS_ALL */	uint8_t xact_pos;	/** Set when the host channel does a short read. */	uint8_t short_read;	/**	 * Number of requests issued for this channel since it was assigned to	 * the current transfer (not counting PINGs).	 */	uint8_t requests;	/**	 * Queue Head for the transfer being processed by this channel.	 */	struct dwc_otg_qh *qh;	/** @} */	/** Entry in list of host channels. */	struct list_head	hc_list_entry;} dwc_hc_t;/** * The following parameters may be specified when starting the module. These * parameters define how the DWC_otg controller should be configured. * Parameter values are passed to the CIL initialization function * dwc_otg_cil_init. */typedef struct dwc_otg_core_params{	int32_t opt;#define dwc_param_opt_default 1	/**	 * Specifies the OTG capabilities. The driver will automatically	 * detect the value for this parameter if none is specified.	 * 0 - HNP and SRP capable (default)	 * 1 - SRP Only capable	 * 2 - No HNP/SRP capable	 */	int32_t otg_cap;#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE	0#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE	1#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE	2#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE	/**	 * Specifies whether to use slave or DMA mode for accessing the data	 * FIFOs. The driver will automatically detect the value for this	 * parameter if none is specified.	 * 0 - Slave	 * 1 - DMA (default, if available)	 */	int32_t dma_enable;#define dwc_param_dma_enable_default 1	/**	 * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data	 * FIFOs in device mode. The driver will automatically detect the value for this	 * parameter if none is specified.	 * 0 - address DMA	 * 1 - DMA Descriptor(default, if available)	 */	int32_t dma_desc_enable;#define dwc_param_dma_desc_enable_default 0	/** The DMA Burst size (applicable only for External DMA	 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)	 */	int32_t dma_burst_size;	 /* Translate this to GAHBCFG values */#define dwc_param_dma_burst_size_default 32	/**	 * Specifies the maximum speed of operation in host and device mode.	 * The actual speed depends on the speed of the attached device and	 * the value of phy_type. The actual speed depends on the speed of the	 * attached device.	 * 0 - High Speed (default)	 * 1 - Full Speed	 */	int32_t speed;#define dwc_param_speed_default 0#define DWC_SPEED_PARAM_HIGH 0#define DWC_SPEED_PARAM_FULL 1	/** Specifies whether low power mode is supported when attached	 *	to a Full Speed or Low Speed device in host mode.	 * 0 - Don't support low power mode (default)	 * 1 - Support low power mode	 */	int32_t host_support_fs_ls_low_power;#define dwc_param_host_support_fs_ls_low_power_default 0	/** Specifies the PHY clock rate in low power mode when connected to a	 * Low Speed device in host mode. This parameter is applicable only if	 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled.	 If PHY_TYPE is set to FS	 * then defaults to 6 MHZ otherwise 48 MHZ.	 *	 * 0 - 48 MHz	 * 1 - 6 MHz	 */	int32_t host_ls_low_power_phy_clk;#define dwc_param_host_ls_low_power_phy_clk_default 0#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1	/**	 * 0 - Use cC FIFO size parameters	 * 1 - Allow dynamic FIFO sizing (default)	 */	int32_t enable_dynamic_fifo;#define dwc_param_enable_dynamic_fifo_default 1	/** Total number of 4-byte words in the data FIFO memory. This	 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic	 * Tx FIFOs.	 * 32 to 32768 (default 8192)	 * Note: The total FIFO memory depth in the FPGA configuration is 8192.	 */	int32_t data_fifo_size;#define dwc_param_data_fifo_size_default 8192	/** Number of 4-byte words in the Rx FIFO in device mode when dynamic	 * FIFO sizing is enabled.	 * 16 to 32768 (default 1064)	 */	int32_t dev_rx_fifo_size;#define dwc_param_dev_rx_fifo_size_default 1064	/** Number of 4-byte words in the non-periodic Tx FIFO in device mode	 * when dynamic FIFO sizing is enabled.	 * 16 to 32768 (default 1024)	 */	int32_t dev_nperio_tx_fifo_size;#define dwc_param_dev_nperio_tx_fifo_size_default 1024	/** Number of 4-byte words in each of the periodic Tx FIFOs in device	 * mode when dynamic FIFO sizing is enabled.	 * 4 to 768 (default 256)	 */	uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];#define dwc_param_dev_perio_tx_fifo_size_default 256	/** Number of 4-byte words in the Rx FIFO in host mode when dynamic	 * FIFO sizing is enabled.	 * 16 to 32768 (default 1024)	 */	int32_t host_rx_fifo_size;#define dwc_param_host_rx_fifo_size_default 1024		/** Number of 4-byte words in the non-periodic Tx FIFO in host mode	 * when Dynamic FIFO sizing is enabled in the core.	 * 16 to 32768 (default 1024)	 */	int32_t host_nperio_tx_fifo_size;#define dwc_param_host_nperio_tx_fifo_size_default 1024	/** Number of 4-byte words in the host periodic Tx FIFO when dynamic	 * FIFO sizing is enabled.	 * 16 to 32768 (default 1024)	 */	int32_t host_perio_tx_fifo_size;#define dwc_param_host_perio_tx_fifo_size_default 1024	/** The maximum transfer size supported in bytes.	 * 2047 to 65,535  (default 65,535)	 */	int32_t max_transfer_size;#define dwc_param_max_transfer_size_default 65535	/** The maximum number of packets in a transfer.	 * 15 to 511  (default 511)	 */	int32_t max_packet_count;#define dwc_param_max_packet_count_default 511	/** The number of host channel registers to use.	 * 1 to 16 (default 12)	 * Note: The FPGA configuration supports a maximum of 12 host channels.	 */	int32_t host_channels;#define dwc_param_host_channels_default 12	/** The number of endpoints in addition to EP0 available for device	 * mode operations.	 * 1 to 15 (default 6 IN and OUT)	 * Note: The FPGA configuration supports a maximum of 6 IN and OUT	 * endpoints in addition to EP0.	 */