//////////////////////////////////////////////////////////////////////////                                                                    //  Abstract: Basing on opencore of the des,I construct 3des.                                                    
//            3eds mode is DES-DED mode.//
//  Module  : des3_inv_cipher                                //                                                                    //  Version : ver 01.00                                  //                                                                    //  Modification History:                                            //  Date By         Change Description                         //  ----------------------------------------------------------------- //  2008/08/06  jackie                                            
//  YYYY/MM/DD  author     Revision content                           
//                                                                    ////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module des3_inv_cipher(invdataout,invdone,datain,key1,key2,key3,inven,des3,rst,clk);
output  [63:0]  invdataout;
output          invdone;
input  [63:0]   datain;
input  [55:0]   key1;
input  [55:0]   key2;
input  [55:0]   key3;
input           inven;
input           des3;
input           rst;
input           clk;

parameter delay = 1'b1;

reg [3:0] cnt_1;
reg [3:0] cnt_2;
reg [3:0] cnt_3;
reg load_1;
reg load_2;
reg load_3;
reg en_delay;
reg done_1;
reg done_2;
reg done_3;
reg [63:0] des2_in;
reg [63:0] des3_in;
reg [63:0] des3_data_out;

wire [63:0] des3_out;
wire [63:0] des1_out;
wire [63:0] des2_out;
wire start;
wire [55:0] key_1;

always @(posedge clk)
  if (rst)
     en_delay <= #delay 1'b0;
  else 
     en_delay <= #delay inven;

assign start = inven&&(!en_delay); 

//E      
always @(posedge clk)
  if (rst)
     load_1 <= #delay 1'b0;      
  else if(start)
     load_1 <= #delay 1'b1;
  else if (done_1)
     load_1 <= #delay 1'b0;     
     
always @(posedge clk)
  if (rst)
     cnt_1 <= #delay 4'b0;  
  else if(load_1)
     cnt_1 <= #delay cnt_1+1;
  else
     cnt_1 <= #delay 4'b0;

always @(posedge clk)
   if (rst)
     done_1 <= #delay 1'b0;
   else if(cnt_1==14)
     done_1 <= #delay 1'b1;
   else 
     done_1 <= #delay 1'b0;

//D
always @(posedge clk)
  if (rst)
     load_2 <= #delay 1'b0;      
  else if(done_1&&des3)
     load_2 <= #delay 1'b1;
  else if (done_2)
     load_2 <= #delay 1'b0;  

always @(posedge clk)
  if (rst)
     cnt_2 <= #delay 4'b0;  
  else if(load_2)
     cnt_2 <= #delay cnt_2+1;
  else
     cnt_2 <= #delay 4'b0;

always @(posedge clk)
   if (rst)
     done_2 <= #delay 1'b0;
   else if(cnt_2==14)
     done_2 <= #delay 1'b1;
   else 
     done_2 <= #delay 1'b0;

//E
always @(posedge clk)
  if (rst)
     load_3 <= #delay 1'b0;      
  else if(done_2)
     load_3 <= #delay 1'b1;
  else if(done_3)
     load_3 <= #delay 1'b0;  

always @(posedge clk)
  if (rst)
     cnt_3 <= #delay 4'b0;  
  else if(load_3)
     cnt_3 <= #delay cnt_3+1;
  else
     cnt_3 <= #delay 4'b0;

always @(posedge clk)
   if (rst)
     done_3 <= #delay 1'b0;
   else if(cnt_3==14)
     done_3 <= #delay 1'b1;
   else 
     done_3 <= #delay 1'b0;

//data output
always @(posedge clk)
  if(rst)
      des2_in <= #delay 64'b0;
  else if(done_1) 
      des2_in <= #delay des1_out;

always @(posedge clk)
  if(rst)
      des3_in <= #delay 64'b0;
  else if(done_2) 
      des3_in <= #delay des2_out;
      
always @(posedge clk)
  if(rst)
      des3_data_out <= #delay 64'b0;
  else if(done_3) 
      des3_data_out <= #delay des3_out;      
            

//DECODE mode
des_inv_cipher inv_cipher_dut1(.desOut(des1_out), .desIn(datain), .key(key_1), .roundSel(cnt_1), .rst(rst), .clk(clk));
des_cipher cipher_dut2(.desOut(des2_out), .desIn(des2_in), .key(key2), .roundSel(cnt_2), .rst(rst), .clk(clk));
des_inv_cipher inv_cipher_dut3(.desOut(des3_out), .desIn(des3_in), .key(key1), .roundSel(cnt_3), .rst(rst), .clk(clk));

//MUX 3des or des
assign invdataout = des3 ? des3_data_out : des2_in ;
assign invdone  = des3 ? done_3:done_1;
assign key_1= des3 ? key3:key1;

endmodule