?? count.rpt
字號(hào):
count
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
66 - - B -- OUTPUT 0 1 0 0 HOUR0
6 - - - 04 OUTPUT 0 1 0 0 HOUR1
22 - - B -- OUTPUT 0 1 0 0 HOUR2
64 - - B -- OUTPUT 0 1 0 0 HOUR3
25 - - B -- OUTPUT 0 1 0 0 M_1MIN0
21 - - B -- OUTPUT 0 1 0 0 M_1MIN1
9 - - - 02 OUTPUT 0 1 0 0 M_1MIN2
65 - - B -- OUTPUT 0 1 0 0 M_1MIN3
67 - - B -- OUTPUT 0 1 0 0 M_10MIN0
23 - - B -- OUTPUT 0 1 0 0 M_10MIN1
5 - - - 05 OUTPUT 0 1 0 0 M_10MIN2
24 - - B -- OUTPUT 0 1 0 0 M_10MIN3
72 - - A -- OUTPUT 0 1 0 0 S_1MS0
69 - - A -- OUTPUT 0 1 0 0 S_1MS1
71 - - A -- OUTPUT 0 1 0 0 S_1MS2
73 - - A -- OUTPUT 0 1 0 0 S_1MS3
35 - - - 06 OUTPUT 0 1 0 0 S_1S0
29 - - C -- OUTPUT 0 1 0 0 S_1S1
30 - - C -- OUTPUT 0 1 0 0 S_1S2
28 - - C -- OUTPUT 0 1 0 0 S_1S3
59 - - C -- OUTPUT 0 1 0 0 S_10MS0
61 - - C -- OUTPUT 0 1 0 0 S_10MS1
58 - - C -- OUTPUT 0 1 0 0 S_10MS2
79 - - - 24 OUTPUT 0 1 0 0 S_10MS3
19 - - A -- OUTPUT 0 1 0 0 S_10S0
17 - - A -- OUTPUT 0 1 0 0 S_10S1
18 - - A -- OUTPUT 0 1 0 0 S_10S2
16 - - A -- OUTPUT 0 1 0 0 S_10S3
27 - - C -- OUTPUT 0 1 0 0 S_100MS0
83 - - - 13 OUTPUT 0 1 0 0 S_100MS1
47 - - - 14 OUTPUT 0 1 0 0 S_100MS2
60 - - C -- OUTPUT 0 1 0 0 S_100MS3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\new\count.rpt
count
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 01 AND2 0 3 0 1 |CDU6:U5|LPM_ADD_SUB:81|addcore:adder|:59
- 4 - A 01 OR2 0 3 0 1 |CDU6:U5|LPM_ADD_SUB:81|addcore:adder|:68
- 4 - B 02 DFFE 1 2 0 5 |CDU6:U5|:4
- 1 - A 01 DFFE 1 3 1 1 |CDU6:U5|SCOUNT63 (|CDU6:U5|:10)
- 5 - A 01 DFFE 1 3 1 3 |CDU6:U5|SCOUNT62 (|CDU6:U5|:11)
- 3 - A 01 DFFE 1 3 1 3 |CDU6:U5|SCOUNT61 (|CDU6:U5|:12)
- 7 - A 01 DFFE 1 1 1 4 |CDU6:U5|SCOUNT60 (|CDU6:U5|:13)
- 2 - A 01 AND2 0 4 0 4 |CDU6:U5|:54
- 8 - B 05 AND2 0 3 0 1 |CDU6:U7|LPM_ADD_SUB:81|addcore:adder|:59
- 7 - B 05 OR2 0 3 0 1 |CDU6:U7|LPM_ADD_SUB:81|addcore:adder|:68
- 4 - B 04 DFFE 1 2 0 4 |CDU6:U7|:4
- 6 - B 05 DFFE 1 3 1 1 |CDU6:U7|SCOUNT63 (|CDU6:U7|:10)
- 5 - B 05 DFFE 1 3 1 3 |CDU6:U7|SCOUNT62 (|CDU6:U7|:11)
- 4 - B 05 DFFE 1 3 1 3 |CDU6:U7|SCOUNT61 (|CDU6:U7|:12)
- 1 - B 05 DFFE 1 1 1 4 |CDU6:U7|SCOUNT60 (|CDU6:U7|:13)
- 3 - B 05 AND2 0 4 0 4 |CDU6:U7|:54
- 6 - A 23 AND2 0 3 0 1 |CDU10:UL|LPM_ADD_SUB:82|addcore:adder|:59
- 2 - A 23 OR2 0 3 0 1 |CDU10:UL|LPM_ADD_SUB:82|addcore:adder|:68
- 1 - C 24 DFFE + 1 1 0 5 |CDU10:UL|:4
- 1 - A 23 DFFE + 1 2 1 1 |CDU10:UL|SCOUNT103 (|CDU10:UL|:10)
- 4 - A 23 DFFE + 1 2 1 3 |CDU10:UL|SCOUNT102 (|CDU10:UL|:11)
- 8 - A 23 DFFE + 1 2 1 3 |CDU10:UL|SCOUNT101 (|CDU10:UL|:12)
- 3 - A 23 DFFE + 1 0 1 4 |CDU10:UL|SCOUNT100 (|CDU10:UL|:13)
- 5 - A 23 AND2 0 4 0 4 |CDU10:UL|:54
- 5 - C 24 AND2 0 3 0 1 |CDU10:U2|LPM_ADD_SUB:82|addcore:adder|:59
- 4 - C 24 OR2 0 3 0 1 |CDU10:U2|LPM_ADD_SUB:82|addcore:adder|:68
- 5 - C 14 DFFE 1 2 0 5 |CDU10:U2|:4
- 7 - C 24 DFFE 1 3 1 1 |CDU10:U2|SCOUNT103 (|CDU10:U2|:10)
- 6 - C 24 DFFE 1 3 1 3 |CDU10:U2|SCOUNT102 (|CDU10:U2|:11)
- 2 - C 24 DFFE 1 3 1 3 |CDU10:U2|SCOUNT101 (|CDU10:U2|:12)
- 8 - C 24 DFFE 1 1 1 4 |CDU10:U2|SCOUNT100 (|CDU10:U2|:13)
- 3 - C 24 AND2 0 4 0 4 |CDU10:U2|:54
- 7 - C 14 AND2 0 3 0 1 |CDU10:U3|LPM_ADD_SUB:82|addcore:adder|:59
- 6 - C 14 OR2 0 3 0 1 |CDU10:U3|LPM_ADD_SUB:82|addcore:adder|:68
- 1 - C 06 DFFE 1 2 0 5 |CDU10:U3|:4
- 4 - C 14 DFFE 1 3 1 1 |CDU10:U3|SCOUNT103 (|CDU10:U3|:10)
- 2 - C 14 DFFE 1 3 1 3 |CDU10:U3|SCOUNT102 (|CDU10:U3|:11)
- 8 - C 14 DFFE 1 3 1 3 |CDU10:U3|SCOUNT101 (|CDU10:U3|:12)
- 1 - C 14 DFFE 1 1 1 4 |CDU10:U3|SCOUNT100 (|CDU10:U3|:13)
- 3 - C 14 AND2 0 4 0 4 |CDU10:U3|:54
- 8 - C 06 AND2 0 3 0 1 |CDU10:U4|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - C 06 OR2 0 3 0 1 |CDU10:U4|LPM_ADD_SUB:82|addcore:adder|:68
- 8 - A 01 DFFE 1 2 0 5 |CDU10:U4|:4
- 2 - C 06 DFFE 1 3 1 1 |CDU10:U4|SCOUNT103 (|CDU10:U4|:10)
- 6 - C 06 DFFE 1 3 1 3 |CDU10:U4|SCOUNT102 (|CDU10:U4|:11)
- 5 - C 06 DFFE 1 3 1 3 |CDU10:U4|SCOUNT101 (|CDU10:U4|:12)
- 4 - C 06 DFFE 1 1 1 4 |CDU10:U4|SCOUNT100 (|CDU10:U4|:13)
- 3 - C 06 AND2 0 4 0 4 |CDU10:U4|:54
- 8 - B 02 AND2 0 3 0 1 |CDU10:U6|LPM_ADD_SUB:82|addcore:adder|:59
- 6 - B 02 OR2 0 3 0 1 |CDU10:U6|LPM_ADD_SUB:82|addcore:adder|:68
- 2 - B 05 DFFE 1 2 0 5 |CDU10:U6|:4
- 5 - B 02 DFFE 1 3 1 1 |CDU10:U6|SCOUNT103 (|CDU10:U6|:10)
- 2 - B 02 DFFE 1 3 1 3 |CDU10:U6|SCOUNT102 (|CDU10:U6|:11)
- 1 - B 02 DFFE 1 3 1 3 |CDU10:U6|SCOUNT101 (|CDU10:U6|:12)
- 7 - B 02 DFFE 1 1 1 4 |CDU10:U6|SCOUNT100 (|CDU10:U6|:13)
- 3 - B 02 AND2 0 4 0 4 |CDU10:U6|:54
- 8 - B 04 AND2 0 3 0 1 |CDU10:U8|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - B 04 OR2 0 3 0 1 |CDU10:U8|LPM_ADD_SUB:82|addcore:adder|:68
- 6 - B 04 DFFE 1 3 1 1 |CDU10:U8|SCOUNT103 (|CDU10:U8|:10)
- 2 - B 04 DFFE 1 3 1 3 |CDU10:U8|SCOUNT102 (|CDU10:U8|:11)
- 1 - B 04 DFFE 1 3 1 3 |CDU10:U8|SCOUNT101 (|CDU10:U8|:12)
- 3 - B 04 DFFE 1 1 1 4 |CDU10:U8|SCOUNT100 (|CDU10:U8|:13)
- 5 - B 04 OR2 ! 0 4 0 3 |CDU10:U8|:54
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\new\count.rpt
count
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 5/ 48( 10%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 6/ 96( 6%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 3/ 96( 3%) 3/ 48( 6%) 7/ 48( 14%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\new\count.rpt
count
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |CDU6:U5|:4
DFF 6 |CDU10:UL|:4
DFF 6 |CDU10:U2|:4
DFF 6 |CDU10:U3|:4
DFF 6 |CDU10:U4|:4
DFF 6 |CDU10:U6|:4
DFF 5 |CDU6:U7|:4
INPUT 5 CLK
Device-Specific Information: c:\new\count.rpt
count
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 39 CLR
Device-Specific Information: c:\new\count.rpt
count
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
EN : INPUT;
-- Node name is 'HOUR0'
-- Equation name is 'HOUR0', type is output
HOUR0 = _LC3_B4;
-- Node name is 'HOUR1'
-- Equation name is 'HOUR1', type is output
HOUR1 = _LC1_B4;
-- Node name is 'HOUR2'
-- Equation name is 'HOUR2', type is output
HOUR2 = _LC2_B4;
-- Node name is 'HOUR3'
-- Equation name is 'HOUR3', type is output
HOUR3 = _LC6_B4;
-- Node name is 'M_1MIN0'
-- Equation name is 'M_1MIN0', type is output
M_1MIN0 = _LC7_B2;
-- Node name is 'M_1MIN1'
-- Equation name is 'M_1MIN1', type is output
M_1MIN1 = _LC1_B2;
-- Node name is 'M_1MIN2'
-- Equation name is 'M_1MIN2', type is output
M_1MIN2 = _LC2_B2;
-- Node name is 'M_1MIN3'
-- Equation name is 'M_1MIN3', type is output
M_1MIN3 = _LC5_B2;
-- Node name is 'M_10MIN0'
-- Equation name is 'M_10MIN0', type is output
M_10MIN0 = _LC1_B5;
-- Node name is 'M_10MIN1'
-- Equation name is 'M_10MIN1', type is output
M_10MIN1 = _LC4_B5;
-- Node name is 'M_10MIN2'
-- Equation name is 'M_10MIN2', type is output
M_10MIN2 = _LC5_B5;
-- Node name is 'M_10MIN3'
-- Equation name is 'M_10MIN3', type is output
M_10MIN3 = _LC6_B5;
-- Node name is 'S_1MS0'
-- Equation name is 'S_1MS0', type is output
S_1MS0 = _LC3_A23;
-- Node name is 'S_1MS1'
-- Equation name is 'S_1MS1', type is output
S_1MS1 = _LC8_A23;
-- Node name is 'S_1MS2'
-- Equation name is 'S_1MS2', type is output
S_1MS2 = _LC4_A23;
-- Node name is 'S_1MS3'
-- Equation name is 'S_1MS3', type is output
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