?? mb.rpt
字號:
Project Information c:\trangeaclock2\mb.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/28/2008 00:06:00
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MB
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
mb EPF10K20TC144-4 3 16 0 0 0 % 133 11 %
User Pins: 3 16 0
Project Information c:\trangeaclock2\mb.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
mb@55 CLK
mb@41 CLR
mb@72 LED0
mb@73 LED1
mb@78 LED2
mb@79 LED3
mb@80 LED4
mb@81 LED5
mb@82 LED6
mb@42 SP
Project Information c:\trangeaclock2\mb.rpt
** FILE HIERARCHY **
|ctrl:U0|
|cb10:U1|
|cb10:U1|lpm_add_sub:54|
|cb10:U1|lpm_add_sub:54|addcore:adder|
|cb10:U1|lpm_add_sub:54|altshift:result_ext_latency_ffs|
|cb10:U1|lpm_add_sub:54|altshift:carry_ext_latency_ffs|
|cb10:U1|lpm_add_sub:54|altshift:oflow_ext_latency_ffs|
|count:U2|
|count:U2|cdu10:UL|
|count:U2|cdu10:UL|lpm_add_sub:82|
|count:U2|cdu10:UL|lpm_add_sub:82|addcore:adder|
|count:U2|cdu10:UL|lpm_add_sub:82|altshift:result_ext_latency_ffs|
|count:U2|cdu10:UL|lpm_add_sub:82|altshift:carry_ext_latency_ffs|
|count:U2|cdu10:UL|lpm_add_sub:82|altshift:oflow_ext_latency_ffs|
|count:U2|cdu10:U2|
|count:U2|cdu10:U2|lpm_add_sub:82|
|count:U2|cdu10:U2|lpm_add_sub:82|addcore:adder|
|count:U2|cdu10:U2|lpm_add_sub:82|altshift:result_ext_latency_ffs|
|count:U2|cdu10:U2|lpm_add_sub:82|altshift:carry_ext_latency_ffs|
|count:U2|cdu10:U2|lpm_add_sub:82|altshift:oflow_ext_latency_ffs|
|count:U2|cdu10:U3|
|count:U2|cdu10:U3|lpm_add_sub:82|
|count:U2|cdu10:U3|lpm_add_sub:82|addcore:adder|
|count:U2|cdu10:U3|lpm_add_sub:82|altshift:result_ext_latency_ffs|
|count:U2|cdu10:U3|lpm_add_sub:82|altshift:carry_ext_latency_ffs|
|count:U2|cdu10:U3|lpm_add_sub:82|altshift:oflow_ext_latency_ffs|
|count:U2|cdu10:U4|
|count:U2|cdu10:U4|lpm_add_sub:82|
|count:U2|cdu10:U4|lpm_add_sub:82|addcore:adder|
|count:U2|cdu10:U4|lpm_add_sub:82|altshift:result_ext_latency_ffs|
|count:U2|cdu10:U4|lpm_add_sub:82|altshift:carry_ext_latency_ffs|
|count:U2|cdu10:U4|lpm_add_sub:82|altshift:oflow_ext_latency_ffs|
|count:U2|cdu6:U5|
|count:U2|cdu6:U5|lpm_add_sub:81|
|count:U2|cdu6:U5|lpm_add_sub:81|addcore:adder|
|count:U2|cdu6:U5|lpm_add_sub:81|altshift:result_ext_latency_ffs|
|count:U2|cdu6:U5|lpm_add_sub:81|altshift:carry_ext_latency_ffs|
|count:U2|cdu6:U5|lpm_add_sub:81|altshift:oflow_ext_latency_ffs|
|count:U2|cdu10:U6|
|count:U2|cdu10:U6|lpm_add_sub:82|
|count:U2|cdu10:U6|lpm_add_sub:82|addcore:adder|
|count:U2|cdu10:U6|lpm_add_sub:82|altshift:result_ext_latency_ffs|
|count:U2|cdu10:U6|lpm_add_sub:82|altshift:carry_ext_latency_ffs|
|count:U2|cdu10:U6|lpm_add_sub:82|altshift:oflow_ext_latency_ffs|
|count:U2|cdu6:U7|
|count:U2|cdu6:U7|lpm_add_sub:81|
|count:U2|cdu6:U7|lpm_add_sub:81|addcore:adder|
|count:U2|cdu6:U7|lpm_add_sub:81|altshift:result_ext_latency_ffs|
|count:U2|cdu6:U7|lpm_add_sub:81|altshift:carry_ext_latency_ffs|
|count:U2|cdu6:U7|lpm_add_sub:81|altshift:oflow_ext_latency_ffs|
|count:U2|cdu10:U8|
|count:U2|cdu10:U8|lpm_add_sub:82|
|count:U2|cdu10:U8|lpm_add_sub:82|addcore:adder|
|count:U2|cdu10:U8|lpm_add_sub:82|altshift:result_ext_latency_ffs|
|count:U2|cdu10:U8|lpm_add_sub:82|altshift:carry_ext_latency_ffs|
|count:U2|cdu10:U8|lpm_add_sub:82|altshift:oflow_ext_latency_ffs|
|mulx:U3|
|mulx:U3|lpm_add_sub:114|
|mulx:U3|lpm_add_sub:114|addcore:adder|
|mulx:U3|lpm_add_sub:114|altshift:result_ext_latency_ffs|
|mulx:U3|lpm_add_sub:114|altshift:carry_ext_latency_ffs|
|mulx:U3|lpm_add_sub:114|altshift:oflow_ext_latency_ffs|
|bcd7:U4|
Device-Specific Information: c:\trangeaclock2\mb.rpt
mb
***** Logic for device 'mb' compiled without errors.
Device: EPF10K20TC144-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S G G G G V S S S S S S S S S S S S S
E E E E E G E E E V E E E E G E N N N N C E E E E E E E V E E E E E E
R R R R R N R R S R C R R R R N R D D D D C R R R R R R R C R R R R R R
V V V V V D V V E V C V V V V D V I I I I I V V V V V V V C V V V V V V
E E E E E I E E G E I E E E E I E N N N N N E E E E E E E I E E E E E E
D D D D D O D D 1 D O D D D D O D T T T T T D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K20TC144-4 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | LED6
RESERVED | 28 81 | LED5
RESERVED | 29 80 | LED4
OUTBCD1 | 30 79 | LED3
OUTBCD3 | 31 78 | LED2
OUTBCD2 | 32 77 | ^MSEL0
OUTBCD0 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | LED1
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R S R G C S R R V R R R R G R V V G C G G G S E V R R R C G R R R R V L
E E E N L P E E C E E E E N E C C N L N N N E N C E E E O N E E E E C E
S G S D R S S C S S S S D S C C D K D D D G C S S S D S S S S C D
E 0 E I E E I E E E E I E I I I I I I 2 I E E E I E E E E I 0
R R O R R O R R R R O R N N N N N N O R R R O R R R R O
V V V V V V V V V T T T T T T V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\trangeaclock2\mb.rpt
mb
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B10 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 0/22( 0%)
F1 6/ 8( 75%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 4/22( 18%)
F4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F6 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 13/22( 59%)
F7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F9 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F11 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
F13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F16 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 18/22( 81%)
F17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -