LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
ENTITY  MB  IS  
    PORT(SP,reback,CLR,CLK:IN   STD_LOGIC;
          CO,EN:    OUT  STD_LOGIC;
          LED:      OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);     
          OUTBCD:   OUT  STD_LOGIC_VECTOR(3 DOWNTO 0); 
          SEG:      OUT  STD_LOGIC_VECTOR(2 DOWNTO 0));
END  MB;
ARCHITECTURE  ART  OF  MB IS
       COMPONENT  CTRL
       PORT(CLR,CLK,SP:IN   STD_LOGIC;
                    EN:OUT  STD_LOGIC);
       END  COMPONENT;
       COMPONENT  CB10
       PORT(CLK:IN  STD_LOGIC;
             CO:OUT  STD_LOGIC);
       END  COMPONENT;
       COMPONENT  COUNT
              PORT(CLK,CLR,EN,reback:IN  STD_LOGIC;	
                    S_1MS:    OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);                   
                    S_10MS:   OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);     	
                    S_100MS:  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);                    
                    S_1S:     OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                    S_10S:    OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                    M_1MIN:   OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                    M_10MIN:  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                       HOUR:  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0));
END  COMPONENT;
COMPONENT  BCD7
    PORT(BCD:IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
          LED:OUT  STD_LOGIC_VECTOR(6 DOWNTO 0));
END  COMPONENT;
COMPONENT  MULX
      PORT(CLK,CLR,EN: IN  STD_LOGIC;            	
            S_1MS:     IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
	        S_10MS:    IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            S_100MS:   IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            S_1S:      IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            S_10S:     IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            M_1MIN:    IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            M_10MIN:   IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            HOUR:      IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            OUTBCD:    OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
             SEG:      OUT  STD_LOGIC_VECTOR(2 DOWNTO 0));
END  COMPONENT;
SIGNAL  C,E:STD_LOGIC;
SIGNAL  S_1MS,S_10MS,S_100MS:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL  S_1S,S_10S:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL  M_1MIN,M_10MIN:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL  H:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL  BCD_S: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U0:CTRL   PORT  MAP(CLR,CLK,SP,E);
U1:CB10   PORT  MAP(CLK,C);
U2:COUNT  PORT  MAP(C,CLR,E,reback,S_1MS,S_10MS,S_100MS,S_1S,S_10S,M_1MIN,M_10MIN,H);    
U3:MULX   PORT  MAP(CLK,CLR,E,S_1MS,S_10MS,S_100MS,S_1S,S_10S,M_1MIN,M_10MIN,H,BCD_S,SEG);
U4:BCD7   PORT  MAP(BCD_S,LED);
CO<=C;
EN<=E;
OUTBCD<=BCD_S;
END  ART;