?? case0.vhd
字號:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY case0 IS
PORT ( table_in0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
table_out0 : OUT INTEGER RANGE 0 TO 1358);
END case0;
ARCHITECTURE LCs OF case0 IS
BEGIN
-- This is the DA CASE table for
-- the 4 coefficients: 0, 101, 399, 858
-- automatically generated with dagen.exe -- DO NOT EDIT!
PROCESS (table_in0)
BEGIN
CASE table_in0 IS
WHEN "0000" => table_out0 <= 0;
WHEN "0001" => table_out0 <= 0;
WHEN "0010" => table_out0 <= 101;
WHEN "0011" => table_out0 <= 101;
WHEN "0100" => table_out0 <= 399;
WHEN "0101" => table_out0 <= 399;
WHEN "0110" => table_out0 <= 500;
WHEN "0111" => table_out0 <= 500;
WHEN "1000" => table_out0 <= 858;
WHEN "1001" => table_out0 <= 858;
WHEN "1010" => table_out0 <= 959;
WHEN "1011" => table_out0 <= 959;
WHEN "1100" => table_out0 <= 1257;
WHEN "1101" => table_out0 <= 1257;
WHEN "1110" => table_out0 <= 1358;
WHEN "1111" => table_out0 <= 1358;
WHEN OTHERS => table_out0 <= 0;
END CASE;
END PROCESS;
END LCs;
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