library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package da_package is
	component case0
		port(table_in0: in std_logic_vector(3 downto 0);
			 table_out0: out integer range 0 to 1358);
	end component;
	
	component case1
		port(table_in1: in std_logic_vector(3 downto 0);
			 table_out1: out integer range 0 to 8283);
	end component;
	
	component case2
		port(table_in2: in std_logic_vector(3 downto 0);
			 table_out2: out integer range 0 to 8283);
	end component;
	
	component case3
		port(table_in3: in std_logic_vector(3 downto 0);
			 table_out3: out integer range 0 to 1358);
	end component;
end da_package;

library work;
use work.da_package.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fir_16 is
	port(clk: in std_logic;
		 x_in0,x_in1,x_in2,x_in3,x_in4,x_in5,x_in6,x_in7,
			x_in8,x_in9,x_in10,x_in11,x_in12,x_in13,x_in14,x_in15: in std_logic_vector(3 downto 0);
		 y: out integer range 0 to 65535);
end fir_16;

architecture flex of fir_16 is
	type state_type is (s0,s1);
	signal state: state_type;
	signal x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,
			table_in0,table_in1,table_in2,table_in3: std_logic_vector(3 downto 0);
	signal table_out0,table_out1,table_out2,table_out3: integer range 0 to 65535;
begin
	table_in0<=(x3(0)&x2(0)&x1(0)&x0(0));
	table_in1<=(x7(0)&x6(0)&x5(0)&x4(0));
	table_in2<=(x11(0)&x10(0)&x9(0)&x8(0));
	table_in3<=(x15(0)&x14(0)&x13(0)&x12(0)); 
	process
		variable p1,p2,p3,p4: integer range 0 to 65535;
		variable count: integer range 0 to 4;
	begin
		wait until clk='1';
		case state is
		when s0=>
		state<=s1;
		count:=0;
		p1:=0;p2:=0;p3:=0;p4:=0;
		x15<=x_in15;
		x14<=x_in14;
		x13<=x_in13;
		x12<=x_in12;
		x11<=x_in11;
		x10<=x_in10;
		x9<=x_in9;
		x8<=x_in8;
		x7<=x_in7;
		x6<=x_in6;
		x5<=x_in5;
		x4<=x_in4;
		x3<=x_in3;
		x2<=x_in2;
		x1<=x_in1;
		x0<=x_in0;
	when s1=>
	if count=4 then
		y<=p1+p2+p3+p4;
		state<=s0;
	else
		p1:=p1/2+table_out0*8;
		p2:=p2/2+table_out1*8;
		p3:=p3/2+table_out2*8;
		p4:=p4/2+table_out3*8;
		for k in 0 to 2 loop
			x0(k)<=x0(k+1);
			x1(k)<=x1(k+1);
			x2(k)<=x2(k+1);
			x3(k)<=x3(k+1);
			x4(k)<=x4(k+1);
			x5(k)<=x5(k+1);
			x6(k)<=x6(k+1);
			x7(k)<=x7(k+1);
			x8(k)<=x8(k+1);
			x9(k)<=x9(k+1);
			x10(k)<=x10(k+1);
			x11(k)<=x11(k+1);
			x12(k)<=x12(k+1);
			x13(k)<=x13(k+1);
			x14(k)<=x14(k+1);
			x15(k)<=x15(k+1);
		end loop;
		count:=count+1;state<=s1;
		
		end if;
		end case;
	end process;
	
	LC_Table0:case0
	port map(table_in0=>table_in0,table_out0=>table_out0);
				
	LC_Table1:case1
	port map(table_in1=>table_in1,table_out1=>table_out1);
	
	LC_Table2:case2
	port map(table_in2=>table_in2,table_out2=>table_out2);
	
	LC_Table3:case3
	port map(table_in3=>table_in3,table_out3=>table_out3);
end flex;