#define GPIO_PDDR_FECI2C_3		(0x08)/* Bit definitions and macros for GPIO_PDDR_UART */#define GPIO_PDDR_UART_0		(0x01)#define GPIO_PDDR_UART_1		(0x02)#define GPIO_PDDR_UART_2		(0x04)#define GPIO_PDDR_UART_3		(0x08)#define GPIO_PDDR_UART_4		(0x10)#define GPIO_PDDR_UART_5		(0x20)#define GPIO_PDDR_UART_6		(0x40)#define GPIO_PDDR_UART_7		(0x80)/* Bit definitions and macros for GPIO_PDDR_QSPI */#define GPIO_PDDR_QSPI_0		(0x01)#define GPIO_PDDR_QSPI_1		(0x02)#define GPIO_PDDR_QSPI_2		(0x04)#define GPIO_PDDR_QSPI_3		(0x08)#define GPIO_PDDR_QSPI_4		(0x10)#define GPIO_PDDR_QSPI_5		(0x20)/* Bit definitions and macros for GPIO_PDDR_TIMER */#define GPIO_PDDR_TIMER_0		(0x01)#define GPIO_PDDR_TIMER_1		(0x02)#define GPIO_PDDR_TIMER_2		(0x04)#define GPIO_PDDR_TIMER_3		(0x08)/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */#define GPIO_PDDR_LCDDATAH_0		(0x01)#define GPIO_PDDR_LCDDATAH_1		(0x02)/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */#define GPIO_PDDR_LCDDATAM_0		(0x01)#define GPIO_PDDR_LCDDATAM_1		(0x02)#define GPIO_PDDR_LCDDATAM_2		(0x04)#define GPIO_PDDR_LCDDATAM_3		(0x08)#define GPIO_PDDR_LCDDATAM_4		(0x10)#define GPIO_PDDR_LCDDATAM_5		(0x20)#define GPIO_PDDR_LCDDATAM_6		(0x40)#define GPIO_PDDR_LCDDATAM_7		(0x80)/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */#define GPIO_PDDR_LCDDATAL_0		(0x01)#define GPIO_PDDR_LCDDATAL_1		(0x02)#define GPIO_PDDR_LCDDATAL_2		(0x04)#define GPIO_PDDR_LCDDATAL_3		(0x08)#define GPIO_PDDR_LCDDATAL_4		(0x10)#define GPIO_PDDR_LCDDATAL_5		(0x20)#define GPIO_PDDR_LCDDATAL_6		(0x40)#define GPIO_PDDR_LCDDATAL_7		(0x80)/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */#define GPIO_PDDR_LCDCTLH_0		(0x01)/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */#define GPIO_PDDR_LCDCTLL_0		(0x01)#define GPIO_PDDR_LCDCTLL_1		(0x02)#define GPIO_PDDR_LCDCTLL_2		(0x04)#define GPIO_PDDR_LCDCTLL_3		(0x08)#define GPIO_PDDR_LCDCTLL_4		(0x10)#define GPIO_PDDR_LCDCTLL_5		(0x20)#define GPIO_PDDR_LCDCTLL_6		(0x40)#define GPIO_PDDR_LCDCTLL_7		(0x80)/* Bit definitions and macros for GPIO_PPDSDR_FECH */#define GPIO_PPDSDR_FECH_L0		(0x01)#define GPIO_PPDSDR_FECH_L1		(0x02)#define GPIO_PPDSDR_FECH_L2		(0x04)#define GPIO_PPDSDR_FECH_L3		(0x08)#define GPIO_PPDSDR_FECH_L4		(0x10)#define GPIO_PPDSDR_FECH_L5		(0x20)#define GPIO_PPDSDR_FECH_L6		(0x40)#define GPIO_PPDSDR_FECH_L7		(0x80)/* Bit definitions and macros for GPIO_PPDSDR_SSI */#define GPIO_PPDSDR_SSI_0		(0x01)#define GPIO_PPDSDR_SSI_1		(0x02)#define GPIO_PPDSDR_SSI_2		(0x04)#define GPIO_PPDSDR_SSI_3		(0x08)#define GPIO_PPDSDR_SSI_4		(0x10)/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */#define GPIO_PPDSDR_BUSCTL_0		(0x01)#define GPIO_PPDSDR_BUSCTL_1		(0x02)#define GPIO_PPDSDR_BUSCTL_2		(0x04)#define GPIO_PPDSDR_BUSCTL_3		(0x08)/* Bit definitions and macros for GPIO_PPDSDR_BE */#define GPIO_PPDSDR_BE_0		(0x01)#define GPIO_PPDSDR_BE_1		(0x02)#define GPIO_PPDSDR_BE_2		(0x04)#define GPIO_PPDSDR_BE_3		(0x08)/* Bit definitions and macros for GPIO_PPDSDR_CS */#define GPIO_PPDSDR_CS_1		(0x02)#define GPIO_PPDSDR_CS_2		(0x04)#define GPIO_PPDSDR_CS_3		(0x08)#define GPIO_PPDSDR_CS_4		(0x10)#define GPIO_PPDSDR_CS_5		(0x20)/* Bit definitions and macros for GPIO_PPDSDR_PWM */#define GPIO_PPDSDR_PWM_2		(0x04)#define GPIO_PPDSDR_PWM_3		(0x08)#define GPIO_PPDSDR_PWM_4		(0x10)#define GPIO_PPDSDR_PWM_5		(0x20)/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */#define GPIO_PPDSDR_FECI2C_0		(0x01)#define GPIO_PPDSDR_FECI2C_1		(0x02)#define GPIO_PPDSDR_FECI2C_2		(0x04)#define GPIO_PPDSDR_FECI2C_3		(0x08)/* Bit definitions and macros for GPIO_PPDSDR_UART */#define GPIO_PPDSDR_UART_0		(0x01)#define GPIO_PPDSDR_UART_1		(0x02)#define GPIO_PPDSDR_UART_2		(0x04)#define GPIO_PPDSDR_UART_3		(0x08)#define GPIO_PPDSDR_UART_4		(0x10)#define GPIO_PPDSDR_UART_5		(0x20)#define GPIO_PPDSDR_UART_6		(0x40)#define GPIO_PPDSDR_UART_7		(0x80)/* Bit definitions and macros for GPIO_PPDSDR_QSPI */#define GPIO_PPDSDR_QSPI_0		(0x01)#define GPIO_PPDSDR_QSPI_1		(0x02)#define GPIO_PPDSDR_QSPI_2		(0x04)#define GPIO_PPDSDR_QSPI_3		(0x08)#define GPIO_PPDSDR_QSPI_4		(0x10)#define GPIO_PPDSDR_QSPI_5		(0x20)/* Bit definitions and macros for GPIO_PPDSDR_TIMER */#define GPIO_PPDSDR_TIMER_0		(0x01)#define GPIO_PPDSDR_TIMER_1		(0x02)#define GPIO_PPDSDR_TIMER_2		(0x04)#define GPIO_PPDSDR_TIMER_3		(0x08)/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */#define GPIO_PPDSDR_LCDDATAH_0		(0x01)#define GPIO_PPDSDR_LCDDATAH_1		(0x02)/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */#define GPIO_PPDSDR_LCDDATAM_0		(0x01)#define GPIO_PPDSDR_LCDDATAM_1		(0x02)#define GPIO_PPDSDR_LCDDATAM_2		(0x04)#define GPIO_PPDSDR_LCDDATAM_3		(0x08)#define GPIO_PPDSDR_LCDDATAM_4		(0x10)#define GPIO_PPDSDR_LCDDATAM_5		(0x20)#define GPIO_PPDSDR_LCDDATAM_6		(0x40)#define GPIO_PPDSDR_LCDDATAM_7		(0x80)/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */#define GPIO_PPDSDR_LCDDATAL_0		(0x01)#define GPIO_PPDSDR_LCDDATAL_1		(0x02)#define GPIO_PPDSDR_LCDDATAL_2		(0x04)#define GPIO_PPDSDR_LCDDATAL_3		(0x08)#define GPIO_PPDSDR_LCDDATAL_4		(0x10)#define GPIO_PPDSDR_LCDDATAL_5		(0x20)#define GPIO_PPDSDR_LCDDATAL_6		(0x40)#define GPIO_PPDSDR_LCDDATAL_7		(0x80)/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */#define GPIO_PPDSDR_LCDCTLH_0		(0x01)/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */#define GPIO_PPDSDR_LCDCTLL_0		(0x01)#define GPIO_PPDSDR_LCDCTLL_1		(0x02)#define GPIO_PPDSDR_LCDCTLL_2		(0x04)#define GPIO_PPDSDR_LCDCTLL_3		(0x08)#define GPIO_PPDSDR_LCDCTLL_4		(0x10)#define GPIO_PPDSDR_LCDCTLL_5		(0x20)#define GPIO_PPDSDR_LCDCTLL_6		(0x40)#define GPIO_PPDSDR_LCDCTLL_7		(0x80)/* Bit definitions and macros for GPIO_PCLRR_FECH */#define GPIO_PCLRR_FECH_L0		(0x01)#define GPIO_PCLRR_FECH_L1		(0x02)#define GPIO_PCLRR_FECH_L2		(0x04)#define GPIO_PCLRR_FECH_L3		(0x08)#define GPIO_PCLRR_FECH_L4		(0x10)#define GPIO_PCLRR_FECH_L5		(0x20)#define GPIO_PCLRR_FECH_L6		(0x40)#define GPIO_PCLRR_FECH_L7		(0x80)/* Bit definitions and macros for GPIO_PCLRR_SSI */#define GPIO_PCLRR_SSI_0		(0x01)#define GPIO_PCLRR_SSI_1		(0x02)#define GPIO_PCLRR_SSI_2		(0x04)#define GPIO_PCLRR_SSI_3		(0x08)#define GPIO_PCLRR_SSI_4		(0x10)/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */#define GPIO_PCLRR_BUSCTL_L0		(0x01)#define GPIO_PCLRR_BUSCTL_L1		(0x02)#define GPIO_PCLRR_BUSCTL_L2		(0x04)#define GPIO_PCLRR_BUSCTL_L3		(0x08)/* Bit definitions and macros for GPIO_PCLRR_BE */#define GPIO_PCLRR_BE_0			(0x01)#define GPIO_PCLRR_BE_1			(0x02)#define GPIO_PCLRR_BE_2			(0x04)#define GPIO_PCLRR_BE_3			(0x08)/* Bit definitions and macros for GPIO_PCLRR_CS */#define GPIO_PCLRR_CS_1			(0x02)#define GPIO_PCLRR_CS_2			(0x04)#define GPIO_PCLRR_CS_3			(0x08)#define GPIO_PCLRR_CS_4			(0x10)#define GPIO_PCLRR_CS_5			(0x20)/* Bit definitions and macros for GPIO_PCLRR_PWM */#define GPIO_PCLRR_PWM_2		(0x04)#define GPIO_PCLRR_PWM_3		(0x08)#define GPIO_PCLRR_PWM_4		(0x10)#define GPIO_PCLRR_PWM_5		(0x20)/* Bit definitions and macros for GPIO_PCLRR_FECI2C */#define GPIO_PCLRR_FECI2C_0		(0x01)#define GPIO_PCLRR_FECI2C_1		(0x02)#define GPIO_PCLRR_FECI2C_2		(0x04)#define GPIO_PCLRR_FECI2C_3		(0x08)/* Bit definitions and macros for GPIO_PCLRR_UART */#define GPIO_PCLRR_UART0		(0x01)#define GPIO_PCLRR_UART1		(0x02)#define GPIO_PCLRR_UART2		(0x04)#define GPIO_PCLRR_UART3		(0x08)#define GPIO_PCLRR_UART4		(0x10)#define GPIO_PCLRR_UART5		(0x20)#define GPIO_PCLRR_UART6		(0x40)#define GPIO_PCLRR_UART7		(0x80)/* Bit definitions and macros for GPIO_PCLRR_QSPI */#define GPIO_PCLRR_QSPI0		(0x01)#define GPIO_PCLRR_QSPI1		(0x02)#define GPIO_PCLRR_QSPI2		(0x04)#define GPIO_PCLRR_QSPI3		(0x08)#define GPIO_PCLRR_QSPI4		(0x10)#define GPIO_PCLRR_QSPI5		(0x20)/* Bit definitions and macros for GPIO_PCLRR_TIMER */#define GPIO_PCLRR_TIMER0		(0x01)#define GPIO_PCLRR_TIMER1		(0x02)#define GPIO_PCLRR_TIMER2		(0x04)#define GPIO_PCLRR_TIMER3		(0x08)/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */#define GPIO_PCLRR_LCDDATAH0		(0x01)#define GPIO_PCLRR_LCDDATAH1		(0x02)/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */#define GPIO_PCLRR_LCDDATAM0		(0x01)#define GPIO_PCLRR_LCDDATAM1		(0x02)#define GPIO_PCLRR_LCDDATAM2		(0x04)#define GPIO_PCLRR_LCDDATAM3		(0x08)#define GPIO_PCLRR_LCDDATAM4		(0x10)#define GPIO_PCLRR_LCDDATAM5		(0x20)#define GPIO_PCLRR_LCDDATAM6		(0x40)#define GPIO_PCLRR_LCDDATAM7		(0x80)/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */#define GPIO_PCLRR_LCDDATAL0		(0x01)#define GPIO_PCLRR_LCDDATAL1		(0x02)#define GPIO_PCLRR_LCDDATAL2		(0x04)#define GPIO_PCLRR_LCDDATAL3		(0x08)#define GPIO_PCLRR_LCDDATAL4		(0x10)#define GPIO_PCLRR_LCDDATAL5		(0x20)#define GPIO_PCLRR_LCDDATAL6		(0x40)#define GPIO_PCLRR_LCDDATAL7		(0x80)/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0		(0x01)/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */#define GPIO_PCLRR_LCDCTLL0		(0x01)#define GPIO_PCLRR_LCDCTLL1		(0x02)#define GPIO_PCLRR_LCDCTLL2		(0x04)#define GPIO_PCLRR_LCDCTLL3		(0x08)#define GPIO_PCLRR_LCDCTLL4		(0x10)#define GPIO_PCLRR_LCDCTLL5		(0x20)#define GPIO_PCLRR_LCDCTLL6		(0x40)#define GPIO_PCLRR_LCDCTLL7		(0x80)/* Bit definitions and macros for GPIO_PAR_FEC */#define GPIO_PAR_FEC_MII(x)		(((x)&0x03)<<0)#define GPIO_PAR_FEC_7W(x)		(((x)&0x03)<<2)#define GPIO_PAR_FEC_7W_GPIO		(0x00)#define GPIO_PAR_FEC_7W_URTS1		(0x04)#define GPIO_PAR_FEC_7W_FEC		(0x0C)#define GPIO_PAR_FEC_MII_GPIO		(0x00)#define GPIO_PAR_FEC_MII_UART		(0x01)#define GPIO_PAR_FEC_MII_FEC		(0x03)/* Bit definitions and macros for GPIO_PAR_PWM */#define GPIO_PAR_PWM1(x)		(((x)&0x03)<<0)#define GPIO_PAR_PWM3(x)		(((x)&0x03)<<2)#define GPIO_PAR_PWM5			(0x10)#define GPIO_PAR_PWM7			(0x20)/* Bit definitions and macros for GPIO_PAR_BUSCTL */#define GPIO_PAR_BUSCTL_TS(x)		(((x)&0x03)<<3)#define GPIO_PAR_BUSCTL_RWB		(0x20)#define GPIO_PAR_BUSCTL_TA		(0x40)#define GPIO_PAR_BUSCTL_OE		(0x80)#define GPIO_PAR_BUSCTL_OE_GPIO		(0x00)#define GPIO_PAR_BUSCTL_OE_OE		(0x80)#define GPIO_PAR_BUSCTL_TA_GPIO		(0x00)#define GPIO_PAR_BUSCTL_TA_TA		(0x40)#define GPIO_PAR_BUSCTL_RWB_GPIO	(0x00)#define GPIO_PAR_BUSCTL_RWB_RWB		(0x20)#define GPIO_PAR_BUSCTL_TS_GPIO		(0x00)#define GPIO_PAR_BUSCTL_TS_DACK0	(0x10)#define GPIO_PAR_BUSCTL_TS_TS		(0x18)/* Bit definitions and macros for GPIO_PAR_FECI2C */#define GPIO_PAR_FECI2C_SDA(x)		(((x)&0x03)<<0)#define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x03)<<2)#define GPIO_PAR_FECI2C_MDIO(x)		(((x)&0x03)<<4)#define GPIO_PAR_FECI2C_MDC(x)		(((x)&0x03)<<6)#define GPIO_PAR_FECI2C_MDC_GPIO	(0x00)#define GPIO_PAR_FECI2C_MDC_UTXD2	(0x40)#define GPIO_PAR_FECI2C_MDC_SCL		(0x80)#define GPIO_PAR_FECI2C_MDC_EMDC	(0xC0)#define GPIO_PAR_FECI2C_MDIO_GPIO	(0x00)#define GPIO_PAR_FECI2C_MDIO_URXD2	(0x10)#define GPIO_PAR_FECI2C_MDIO_SDA	(0x20)#define GPIO_PAR_FECI2C_MDIO_EMDIO	(0x30)#define GPIO_PAR_FECI2C_SCL_GPIO	(0x00)#define GPIO_PAR_FECI2C_SCL_UTXD2	(0x04)#define GPIO_PAR_FECI2C_SCL_SCL		(0x0C)#define GPIO_PAR_FECI2C_SDA_GPIO	(0x00)#define GPIO_PAR_FECI2C_SDA_URXD2	(0x02)#define GPIO_PAR_FECI2C_SDA_SDA		(0x03)/* Bit definitions and macros for GPIO_PAR_BE */#define GPIO_PAR_BE0			(0x01)#define GPIO_PAR_BE1			(0x02)#define GPIO_PAR_BE2			(0x04)#define GPIO_PAR_BE3			(0x08)/* Bit definitions and macros for GPIO_PAR_CS */#define GPIO_PAR_CS1			(0x02)#define GPIO_PAR_CS2			(0x04)#define GPIO_PAR_CS3			(0x08)#define GPIO_PAR_CS4			(0x10)#define GPIO_PAR_CS5			(0x20)#define GPIO_PAR_CS1_GPIO		(0x00)#define GPIO_PAR_CS1_SDCS1		(0x01)#define GPIO_PAR_CS1_CS1		(0x03)/* Bit definitions and macros for GPIO_PAR_SSI */#define GPIO_PAR_SSI_MCLK		(0x0080)#define GPIO_PAR_SSI_TXD(x)		(((x)&0x0003)<<8)#define GPIO_PAR_SSI_RXD(x)		(((x)&0x0003)<<10)#define GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<12)#define GPIO_PAR_SSI_BCLK(x)		(((x)&0x0003)<<14)/* Bit definitions and macros for GPIO_PAR_UART */#define GPIO_PAR_UART_TXD0		(0x0001)#define GPIO_PAR_UART_RXD0		(0x0002)#define GPIO_PAR_UART_RTS0		(0x0004)#define GPIO_PAR_UART_CTS0		(0x0008)#define GPIO_PAR_UART_TXD1(x)		(((x)&0x0003)<<4)#define GPIO_PAR_UART_RXD1(x)		(((x)&0x0003)<<6)#define GPIO_PAR_UART_RTS1(x)		(((x)&0x0003)<<8)#define GPIO_PAR_UART_CTS1(x)		(((x)&0x0003)<<10)#define GPIO_PAR_UART_CTS1_GPIO		(0x0000)#define GPIO_PAR_UART_CTS1_SSI_BCLK	(0x0800)#define GPIO_PAR_UART_CTS1_ULPI_D7	(0x0400)#define GPIO_PAR_UART_CTS1_UCTS1	(0x0C00)#define GPIO_PAR_UART_RTS1_GPIO		(0x0000)#define GPIO_PAR_UART_RTS1_SSI_FS	(0x0200)#define GPIO_PAR_UART_RTS1_ULPI_D6	(0x0100)#define GPIO_PAR_UART_RTS1_URTS1	(0x0300)#define GPIO_PAR_UART_RXD1_GPIO		(0x0000)#define GPIO_PAR_UART_RXD1_SSI_RXD	(0x0080)#define GPIO_PAR_UART_RXD1_ULPI_D5	(0x0040)#define GPIO_PAR_UART_RXD1_URXD1	(0x00C0)#define GPIO_PAR_UART_TXD1_GPIO		(0x0000)#define GPIO_PAR_UART_TXD1_SSI_TXD	(0x0020)#define GPIO_PAR_UART_TXD1_ULPI_D4	(0x0010)#define GPIO_PAR_UART_TXD1_UTXD1	(0x0030)/* Bit definitions and macros for GPIO_PAR_QSPI */#define GPIO_PAR_QSPI_SCK(x)		(((x)&0x0003)<<4)#define GPIO_PAR_QSPI_DOUT(x)		(((x)&0x0003)<<6)#define GPIO_PAR_QSPI_DIN(x)		(((x)&0x0003)<<8)#define GPIO_PAR_QSPI_PCS0(x)		(((x)&0x0003)<<10)#define GPIO_PAR_QSPI_PCS1(x)		(((x)&0x0003)<<12)#define GPIO_PAR_QSPI_PCS2(x)		(((x)&0x0003)<<14)/* Bit definitions and macros for GPIO_PAR_TIMER */#define GPIO_PAR_TIN0(x)		(((x)&0x03)<<0)#define GPIO_PAR_TIN1(x)		(((x)&0x03)<<2)#define GPIO_PAR_TIN2(x)		(((x)&0x03)<<4)#define GPIO_PAR_TIN3(x)		(((x)&0x03)<<6)#define GPIO_PAR_TIN3_GPIO		(0x00)#define GPIO_PAR_TIN3_TOUT3		(0x80)#define GPIO_PAR_TIN3_URXD2		(0x40)#define GPIO_PAR_TIN3_TIN3		(0xC0)#define GPIO_PAR_TIN2_GPIO		(0x00)#define GPIO_PAR_TIN2_TOUT2		(0x20)#define GPIO_PAR_TIN2_UTXD2		(0x10)#define GPIO_PAR_TIN2_TIN2		(0x30)#define GPIO_PAR_TIN1_GPIO		(0x00)#define GPIO_PAR_TIN1_TOUT1		(0x08)#define GPIO_PAR_TIN1_DACK1		(0x04)#define GPIO_PAR_TIN1_TIN1		(0x0C)#define GPIO_PAR_TIN0_GPIO		(0x00)#define GPIO_PAR_TIN0_TOUT0		(0x02)#define GPIO_PAR_TIN0_DREQ0		(0x01)#define GPIO_PAR_TIN0_TIN0		(0x03)/* Bit definitions and macros for GPIO_PAR_LCDDATA */#define GPIO_PAR_LCDDATA_LD7_0(x)	((x)&0x03)#define GPIO_PAR_LCDDATA_LD15_8(x)	(((x)&0x03)<<2)#define GPIO_PAR_LCDDATA_LD16(x)	(((x)&0x03)<<4)#define GPIO_PAR_LCDDATA_LD17(x)	(((x)&0x03)<<6)/* Bit definitions and macros for GPIO_PAR_LCDCTL */#define GPIO_PAR_LCDCTL_CLS		(0x0001)