/* * (C) Copyright 2003-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Derived from the MPC8xx FEC driver. * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com> */#include <common.h>#include <mpc512x.h>#include <malloc.h>#include <net.h>#include <miiphy.h>#include "fec.h"DECLARE_GLOBAL_DATA_PTR;#define DEBUG 0#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \	defined(CONFIG_MPC512x_FEC)#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))#error "CONFIG_MII has to be defined!"#endif#if (DEBUG & 0x40)static uint32 local_crc32(char *string, unsigned int crc_value, int len);#endifint fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);static uchar rx_buff[FEC_BUFFER_SIZE];static int rx_buff_idx = 0;/********************************************************************/#if (DEBUG & 0x2)static void mpc512x_fec_phydump (char *devname){	uint16 phyStatus, i;	uint8 phyAddr = CONFIG_PHY_ADDR;	uint8 reg_mask[] = {		/* regs to print: 0...8, 21,27,31 */		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,		0, 0, 0, 0,  0, 1, 0, 0,     0, 0, 0, 1,  0, 0, 0, 1,	};	for (i = 0; i < 32; i++) {		if (reg_mask[i]) {			miiphy_read (devname, phyAddr, i, &phyStatus);			printf ("Mii reg %d: 0x%04x\n", i, phyStatus);		}	}}#endif/********************************************************************/static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec){	int ix;	/*	 * Receive BDs init	 */	for (ix = 0; ix < FEC_RBD_NUM; ix++) {		fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];		fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;		fec->bdBase->rbd[ix].dataLength = 0;	}	/*	 * have the last RBD to close the ring	 */	fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;	fec->rbdIndex = 0;	/*	 * Trasmit BDs init	 */	for (ix = 0; ix < FEC_TBD_NUM; ix++) {		fec->bdBase->tbd[ix].status = 0;	}	/*	 * Have the last TBD to close the ring	 */	fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;	/*	 * Initialize some indices	 */	fec->tbdIndex = 0;	fec->usedTbdIndex = 0;	fec->cleanTbdNum = FEC_TBD_NUM;	return 0;}/********************************************************************/static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd){	/*	 * Reset buffer descriptor as empty	 */	if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))		pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);	else		pRbd->status = FEC_RBD_EMPTY;	pRbd->dataLength = 0;	/*	 * Increment BD count	 */	fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;	/*	 * Now, we have an empty RxBD, notify FEC	 */	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */}/********************************************************************/static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec){	volatile FEC_TBD *pUsedTbd;#if (DEBUG & 0x1)	printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",		fec->cleanTbdNum, fec->usedTbdIndex);#endif	/*	 * process all the consumed TBDs	 */	while (fec->cleanTbdNum < FEC_TBD_NUM) {		pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];		if (pUsedTbd->status & FEC_TBD_READY) {#if (DEBUG & 0x20)			printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);#endif			return;		}		/*		 * clean this buffer descriptor		 */		if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))			pUsedTbd->status = FEC_TBD_WRAP;		else			pUsedTbd->status = 0;		/*		 * update some indeces for a correct handling of the TBD ring		 */		fec->cleanTbdNum++;		fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;	}}/********************************************************************/static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac){	uint8 currByte;			/* byte for which to compute the CRC */	int byte;			/* loop - counter */	int bit;			/* loop - counter */	uint32 crc = 0xffffffff;	/* initial value */	/*	 * The algorithm used is the following:	 * we loop on each of the six bytes of the provided address,	 * and we compute the CRC by left-shifting the previous	 * value by one position, so that each bit in the current	 * byte of the address may contribute the calculation. If	 * the latter and the MSB in the CRC are different, then	 * the CRC value so computed is also ex-ored with the	 * "polynomium generator". The current byte of the address	 * is also shifted right by one bit at each iteration.	 * This is because the CRC generatore in hardware is implemented	 * as a shift-register with as many ex-ores as the radixes	 * in the polynomium. This suggests that we represent the	 * polynomiumm itself as a 32-bit constant.	 */	for (byte = 0; byte < 6; byte++) {		currByte = mac[byte];		for (bit = 0; bit < 8; bit++) {			if ((currByte & 0x01) ^ (crc & 0x01)) {				crc >>= 1;				crc = crc ^ 0xedb88320;			} else {				crc >>= 1;			}			currByte >>= 1;		}	}	crc = crc >> 26;	/*	 * Set individual hash table register	 */	if (crc >= 32) {		fec->eth->iaddr1 = (1 << (crc - 32));		fec->eth->iaddr2 = 0;	} else {		fec->eth->iaddr1 = 0;		fec->eth->iaddr2 = (1 << crc);	}	/*	 * Set physical address	 */	fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];	fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;}/********************************************************************/static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis){	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;#if (DEBUG & 0x1)	printf ("mpc512x_fec_init... Begin\n");#endif	/* Set interrupt mask register */	fec->eth->imask = 0x00000000;	/* Clear FEC-Lite interrupt event register(IEVENT) */	fec->eth->ievent = 0xffffffff;	/* Set transmit fifo watermark register(X_WMRK), default = 64 */	fec->eth->x_wmrk = 0x0;	/* Set Opcode/Pause Duration Register */	fec->eth->op_pause = 0x00010020;	/* Frame length=1522; MII mode */	fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;	/* Half-duplex, heartbeat disabled */	fec->eth->x_cntrl = 0x00000000;	/* Enable MIB counters */	fec->eth->mib_control = 0x0;	/* Setup recv fifo start and buff size */	fec->eth->r_fstart = 0x500;	fec->eth->r_buff_size = FEC_BUFFER_SIZE;	/* Setup BD base addresses */	fec->eth->r_des_start = (uint32)fec->bdBase->rbd;	fec->eth->x_des_start = (uint32)fec->bdBase->tbd;	/* DMA Control */	fec->eth->dma_control = 0xc0000000;	/* Enable FEC */	fec->eth->ecntrl |= 0x00000006;	/* Initilize addresses and status words of BDs */	mpc512x_fec_bd_init (fec);	 /* Descriptor polling active */	fec->eth->r_des_active = 0x01000000;#if (DEBUG & 0x1)	printf("mpc512x_fec_init... Done \n");#endif	return 1;}/********************************************************************/int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis){	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */	int timeout = 1;	uint16 phyStatus;#if (DEBUG & 0x1)	printf ("mpc512x_fec_init_phy... Begin\n");#endif	/*	 * Clear FEC-Lite interrupt event register(IEVENT)	 */	fec->eth->ievent = 0xffffffff;	/*	 * Set interrupt mask register	 */	fec->eth->imask = 0x00000000;	if (fec->xcv_type != SEVENWIRE) {		/*		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock		 * and do not drop the Preamble.		 */		fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;		/*		 * Reset PHY, then delay 300ns		 */		miiphy_write (dev->name, phyAddr, 0x0, 0x8000);		udelay (1000);		if (fec->xcv_type == MII10) {		/*		 * Force 10Base-T, FDX operation		 */#if (DEBUG & 0x2)			printf ("Forcing 10 Mbps ethernet link... ");#endif			miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);			miiphy_write (dev->name, phyAddr, 0x0, 0x0180);			timeout = 20;			do {    /* wait for link status to go down */				udelay (10000);				if ((timeout--) == 0) {#if (DEBUG & 0x2)					printf ("hmmm, should not have waited...");#endif					break;				}				miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);#if (DEBUG & 0x2)				printf ("=");#endif			} while ((phyStatus & 0x0004)); /* !link up */			timeout = 1000;			do {    /* wait for link status to come back up */				udelay (10000);				if ((timeout--) == 0) {					printf ("failed. Link is down.\n");					break;				}				miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);#if (DEBUG & 0x2)				printf ("+");#endif			} while (!(phyStatus & 0x0004)); /* !link up */#if (DEBUG & 0x2)			printf ("done.\n");#endif		} else {	/* MII100 */			/*			 * Set the auto-negotiation advertisement register bits			 */			miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);			/*			 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation			 */			miiphy_write (dev->name, phyAddr, 0x0, 0x1200);			/*			 * Wait for AN completion			 */			timeout = 50000;			do {				udelay (1000);				if ((timeout--) == 0) {#if (DEBUG & 0x2)					printf ("PHY auto neg 0 failed...\n");#endif					return -1;				}				if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {#if (DEBUG & 0x2)					printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);#endif					return -1;				}			} while (!(phyStatus & 0x0004));#if (DEBUG & 0x2)			printf ("PHY auto neg complete! \n");#endif		}	}#if (DEBUG & 0x2)	if (fec->xcv_type != SEVENWIRE)		mpc512x_fec_phydump (dev->name);#endif#if (DEBUG & 0x1)	printf ("mpc512x_fec_init_phy... Done \n");#endif	return 1;}/********************************************************************/static void mpc512x_fec_halt (struct eth_device *dev){	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;