int counter = 0xffff;#if (DEBUG & 0x2)	if (fec->xcv_type != SEVENWIRE)		mpc512x_fec_phydump (dev->name);#endif	/*	 * mask FEC chip interrupts	 */	fec->eth->imask = 0;	/*	 * issue graceful stop command to the FEC transmitter if necessary	 */	fec->eth->x_cntrl |= 0x00000001;	/*	 * wait for graceful stop to register	 */	while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;	/*	 * Disable the Ethernet Controller	 */	fec->eth->ecntrl &= 0xfffffffd;	/*	 * Issue a reset command to the FEC chip	 */	fec->eth->ecntrl |= 0x1;	/*	 * wait at least 16 clock cycles	 */	udelay (10);#if (DEBUG & 0x3)	printf ("Ethernet task stopped\n");#endif}/********************************************************************/static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,		int data_length){	/*	 * This routine transmits one frame.  This routine only accepts	 * 6-byte Ethernet addresses.	 */	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;	volatile FEC_TBD *pTbd;#if (DEBUG & 0x20)	printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);#endif	/*	 * Clear Tx BD ring at first	 */	mpc512x_fec_tbd_scrub (fec);	/*	 * Check for valid length of data.	 */	if ((data_length > 1500) || (data_length <= 0)) {		return -1;	}	/*	 * Check the number of vacant TxBDs.	 */	if (fec->cleanTbdNum < 1) {#if (DEBUG & 0x20)		printf ("No available TxBDs ...\n");#endif		return -1;	}	/*	 * Get the first TxBD to send the mac header	 */	pTbd = &fec->bdBase->tbd[fec->tbdIndex];	pTbd->dataLength = data_length;	pTbd->dataPointer = (uint32)eth_data;	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;	/* Activate transmit Buffer Descriptor polling */	fec->eth->x_des_active = 0x01000000;	/* Descriptor polling active	*/#if (DEBUG & 0x8)	printf ( "+" );#endif	fec->cleanTbdNum -= 1;	/*	 * wait until frame is sent .	 */	while (pTbd->status & FEC_TBD_READY) {		udelay (10);#if (DEBUG & 0x8)		printf ("TDB status = %04x\n", pTbd->status);#endif	}	return 0;}/********************************************************************/static int mpc512x_fec_recv (struct eth_device *dev){	/*	 * This command pulls one frame from the card	 */	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;	volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];	unsigned long ievent;	int frame_length = 0;#if (DEBUG & 0x1)	printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);#endif#if (DEBUG & 0x8)	printf( "-" );#endif	/*	 * Check if any critical events have happened	 */	ievent = fec->eth->ievent;	fec->eth->ievent = ievent;	if (ievent & 0x20060000) {		/* BABT, Rx/Tx FIFO errors */		mpc512x_fec_halt (dev);		mpc512x_fec_init (dev, NULL);		return 0;	}	if (ievent & 0x80000000) {		/* Heartbeat error */		fec->eth->x_cntrl |= 0x00000001;	}	if (ievent & 0x10000000) {		/* Graceful stop complete */		if (fec->eth->x_cntrl & 0x00000001) {			mpc512x_fec_halt (dev);			fec->eth->x_cntrl &= ~0x00000001;			mpc512x_fec_init (dev, NULL);		}	}	if (!(pRbd->status & FEC_RBD_EMPTY)) {		if (!(pRbd->status & FEC_RBD_ERR) &&			((pRbd->dataLength - 4) > 14)) {			/*			 * Get buffer size			 */			if (pRbd->status & FEC_RBD_LAST)				frame_length = pRbd->dataLength - 4;			else				frame_length = pRbd->dataLength;#if (DEBUG & 0x20)			{				int i;				printf ("recv data length 0x%08x data hdr: ",					pRbd->dataLength);				for (i = 0; i < 14; i++)					printf ("%x ", *((uint8*)pRbd->dataPointer + i));				printf("\n");			}#endif			/*			 *  Fill the buffer and pass it to upper layers			 */			memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,				frame_length - rx_buff_idx);			rx_buff_idx = frame_length;			if (pRbd->status & FEC_RBD_LAST) {				NetReceive ((uchar*)rx_buff, frame_length);				rx_buff_idx = 0;			}		}		/*		 * Reset buffer descriptor as empty		 */		mpc512x_fec_rbd_clean (fec, pRbd);	}	/* Try to fill Buffer Descriptors */	fec->eth->r_des_active = 0x01000000;	/* Descriptor polling active */	return frame_length;}/********************************************************************/int mpc512x_fec_initialize (bd_t * bis){	immap_t *im = (immap_t*) CFG_IMMR;	mpc512x_fec_priv *fec;	struct eth_device *dev;	int i;	char *tmp, *end, env_enetaddr[6];	uint32 *reg;	void * bd;	fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));	dev = (struct eth_device *) malloc (sizeof(*dev));	memset (dev, 0, sizeof *dev);	fec->eth = (ethernet_regs *) MPC512X_FEC;# ifndef CONFIG_FEC_10MBIT	fec->xcv_type = MII100;# else	fec->xcv_type = MII10;# endif	dev->priv = (void *)fec;	dev->iobase = MPC512X_FEC;	dev->init = mpc512x_fec_init;	dev->halt = mpc512x_fec_halt;	dev->send = mpc512x_fec_send;	dev->recv = mpc512x_fec_recv;	sprintf (dev->name, "FEC ETHERNET");	eth_register (dev);#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)	miiphy_register (dev->name,			fec512x_miiphy_read, fec512x_miiphy_write);#endif	/*	 * Initialize I\O pins	 */	reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);	for (i = 0; i < 15; i++)		reg[i] = IOCTRL_MUX_FEC | 0x00000001;	im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001;	im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001;	im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001;	/* Clean up space FEC's MIB and FIFO RAM ...*/	memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);	/*	 * Malloc space for BDs  (must be quad word-aligned)	 * this pointer is lost, so cannot be freed	 */	bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);	fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);	memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);	/*	 * Set interrupt mask register	 */	fec->eth->imask = 0x00000000;	/*	 * Clear FEC-Lite interrupt event register(IEVENT)	 */	fec->eth->ievent = 0xffffffff;	/*	 * Try to set the mac address now. The fec mac address is	 * a garbage after reset. When not using fec for booting	 * the Linux fec driver will try to work with this garbage.	 */	tmp = getenv ("ethaddr");	if (tmp) {		for (i=0; i<6; i++) {			env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;			if (tmp)				tmp = (*end) ? end+1 : end;		}		mpc512x_fec_set_hwaddr (fec, env_enetaddr);		fec->eth->gaddr1 = 0x00000000;		fec->eth->gaddr2 = 0x00000000;	}	mpc512x_fec_init_phy (dev, bis);	return 1;}/* MII-interface related functions *//********************************************************************/int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal){	ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;	uint32 reg;		/* convenient holder for the PHY register */	uint32 phy;		/* convenient holder for the PHY */	int timeout = 0xffff;	/*	 * reading from any PHY's register is done by properly	 * programming the FEC's MII data register.	 */	reg = regAddr << FEC_MII_DATA_RA_SHIFT;	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);	/*	 * wait for the related interrupt	 */	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;	if (timeout == 0) {#if (DEBUG & 0x2)		printf ("Read MDIO failed...\n");#endif		return -1;	}	/*	 * clear mii interrupt bit	 */	eth->ievent = 0x00800000;	/*	 * it's now safe to read the PHY's register	 */	*retVal = (uint16) eth->mii_data;	return 0;}/********************************************************************/int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data){	ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;	uint32 reg;		/* convenient holder for the PHY register */	uint32 phy;		/* convenient holder for the PHY */	int timeout = 0xffff;	reg = regAddr << FEC_MII_DATA_RA_SHIFT;	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;	eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |			FEC_MII_DATA_TA | phy | reg | data);	/*	 * wait for the MII interrupt	 */	while ((timeout--) && (!(eth->ievent & 0x00800000))) ;	if (timeout == 0) {#if (DEBUG & 0x2)		printf ("Write MDIO failed...\n");#endif		return -1;	}	/*	 * clear MII interrupt bit	 */	eth->ievent = 0x00800000;	return 0;}#if (DEBUG & 0x40)static uint32 local_crc32 (char *string, unsigned int crc_value, int len){	int i;	char c;	unsigned int crc, count;	/*	 * crc32 algorithm	 */	/*	 * crc = 0xffffffff; * The initialized value should be 0xffffffff	 */	crc = crc_value;	for (i = len; --i >= 0;) {		c = *string++;		for (count = 0; count < 8; count++) {			if ((c & 0x01) ^ (crc & 0x01)) {				crc >>= 1;				crc = crc ^ 0xedb88320;			} else {				crc >>= 1;			}			c >>= 1;		}	}	/*	 * In big endian system, do byte swaping for crc value	 */	 /**/ return crc;}#endif	/* DEBUG */#endif /* CONFIG_MPC512x_FEC */