Notes on the Vibren PXA255 IDP.Chip select usage:CS0 - flashCS1 - alt flash (Mdoc or main flash)CS2 - high speed expansion busCS3 - Media Q, low speed exp busCS4 - low speed exp busCS5 - low speed exp bus  - IDE: offset 0x03000000 (abs: 0x17000000)  - Eth: offset 0x03400000 (abs: 0x17400000)  - core voltage latch: offset 0x03800000 (abs: 0x17800000)  - CPLD: offset 0x03C00000 (abs: 0x17C00000)PCMCIA Power controlMAX1602EE w/ code pulled high (Cirrus code)vx = 5vvy = 3v			Bit pattern			PWR 3,2,1,0vcc	     vpp	A1VCC  A0VCC   A1VPP   A0VPP=====================================================0	     0            0      0       0       0	0x03 (vy)	     0            1      0       1       1	0xB3 (vy)	     3 (vy)       1      0       0       1	0x93 (vy)	     12(12in)     1      0       1       0	0xA5 (vx)	     0            0      1       1       1	0x75 (vx)	     5 (vx)       0      1       0       1	0x55 (vx	     12(12in)     0      1       1       0	0x6Display power sequencing:- VDD applied- within 1sec, activate scanning signals- wait at least 50mS - scanning signals must be active before activating DISPSignal mapping:Schematic            LV8V31 signal name=========================================LCD_ENAVLCD		DISPLCD_PWR			Applies VDD to boardBoth of the above signals are controlled by the CPLD