library ieee;
use ieee.std_logic_1164.all;

entity jicunqi is
port(d,clk,en:in std_logic;
         y:out std_logic);
end jicunqi;

architecture one of jicunqi is
component dchufa
port(clk,d:in std_logic;
          q:out std_logic);
end component;

signal z,b:std_logic;
signal q:std_logic_vector(3 downto 0);
begin
z<=d;
u1:dchufa port map(clk,z,q(0));
u2:dchufa port map(clk,q(0),q(1));
u3:dchufa port map(clk,q(1),q(2));
u4:dchufa port map(clk,q(2),q(3));
process(en,q)
begin
if(en='0')then
   b<='0';
elsif(en='1')then
 if(q="1111")then
   b<='1';
 elsif(q="0000")then
   b<='0'; 
 end if;
end if;
end process;
y<=b;
end one;