{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 14 16:52:28 2009 " "Info: Processing started: Wed Jan 14 16:52:28 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.v " "Warning: Can't analyze file -- file D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file int_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/int_div.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file int_div2.v" { { "Info" "ISGN_ENTITY_NAME" "1 int_div2 " "Info: Found entity 1: int_div2" {  } { { "int_div2.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/int_div2.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiaotongdeng_con.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jiaotongdeng_con.v" { { "Info" "ISGN_ENTITY_NAME" "1 jiaotongdeng_con " "Info: Found entity 1: jiaotongdeng_con" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg_7.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seg_7.v" { { "Info" "ISGN_ENTITY_NAME" "1 seg_7 " "Info: Found entity 1: seg_7" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiaotongdeng.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file jiaotongdeng.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 jiaotongdeng " "Info: Found entity 1: jiaotongdeng" {  } { { "jiaotongdeng.bdf" "" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jiaotongdeng " "Info: Elaborating entity \"jiaotongdeng\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jiaotongdeng_con jiaotongdeng_con:inst3 " "Info: Elaborating entity \"jiaotongdeng_con\" for hierarchy \"jiaotongdeng_con:inst3\"" {  } { { "jiaotongdeng.bdf" "inst3" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 232 432 528 424 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "CS jiaotongdeng_con.v(55) " "Warning (10235): Verilog HDL Always Construct warning at jiaotongdeng_con.v(55): variable \"CS\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 55 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng_con.v(106) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(106): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng_con.v(110) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(110): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng_con.v(133) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(133): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 133 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng_con.v(158) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(158): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng_con.v(162) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(162): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng_con.v(186) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng_con.v(186): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng_con.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng_con.v" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div int_div:inst " "Info: Elaborating entity \"int_div\" for hierarchy \"int_div:inst\"" {  } { { "jiaotongdeng.bdf" "inst" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 224 144 256 320 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg_7 seg_7:inst4 " "Info: Elaborating entity \"seg_7\" for hierarchy \"seg_7:inst4\"" {  } { { "jiaotongdeng.bdf" "inst4" { Schematic "D:/My Documents/quartusII/Verilog/jiaotongdeng/jiaotongdeng.bdf" { { 216 664 808 312 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 seg_7.v(17) " "Warning (10230): Verilog HDL assignment warning at seg_7.v(17): truncated value with size 32 to match size of target (2)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "qh seg_7.v(23) " "Warning (10235): Verilog HDL Always Construct warning at seg_7.v(23): variable \"qh\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 23 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ql seg_7.v(24) " "Warning (10235): Verilog HDL Always Construct warning at seg_7.v(24): variable \"ql\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 24 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "seg_7.v(22) " "Warning (10270): Verilog HDL Case Statement warning at seg_7.v(22): incomplete case statement has no default case item" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 22 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "scan seg_7.v(20) " "Warning (10240): Verilog HDL Always Construct warning at seg_7.v(20): inferring latch(es) for variable \"scan\", which holds its previous value in one or more paths through the always construct" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "temp seg_7.v(20) " "Warning (10240): Verilog HDL Always Construct warning at seg_7.v(20): inferring latch(es) for variable \"temp\", which holds its previous value in one or more paths through the always construct" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "temp\[0\] seg_7.v(20) " "Info (10041): Inferred latch for \"temp\[0\]\" at seg_7.v(20)" {  } { { "seg_7.v" "" { Text "D:/My Documents/quartusII/Verilog/jiaotongdeng/seg_7.v" 20 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}