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taskSRInit {initialize the default task status register (MIPS)} {<b><i>taskSRInit</i>\( \)</b>} {<b><i><a href="./taskArchLib.html#taskSRInit">taskSRInit</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxTas {C-callable atomic test-and-set primitive} {<b><i>vxTas</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxTas">vxTas</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxMemArchProbe {architecture specific part of vxMemProbe} {<b><i>vxMemArchProbe</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxMemArchProbe">vxMemArchProbe</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxMemProbe {probe an address for a bus error} {<b><i>vxMemProbe</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxMemProbe">vxMemProbe</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxMemProbeAsi {probe address in ASI space for bus error (SPARC)} {<b><i>vxMemProbeAsi</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxMemProbeAsi">vxMemProbeAsi</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxSSEnable {enable the superscalar dispatch (MC68060)} {<b><i>vxSSEnable</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxSSEnable">vxSSEnable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxSSDisable {disable the superscalar dispatch (MC68060)} {<b><i>vxSSDisable</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxSSDisable">vxSSDisable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxPowerModeSet {set the power management mode (PowerPC)} {<b><i>vxPowerModeSet</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxPowerModeSet">vxPowerModeSet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxPowerModeGet {get the power management mode (PowerPC)} {<b><i>vxPowerModeGet</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxPowerModeGet">vxPowerModeGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}vxPowerDown {place the processor in reduced-power mode (PowerPC)} {<b><i>vxPowerDown</i>\( \)</b>} {<b><i><a href="./vxLib.html#vxPowerDown">vxPowerDown</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheArchLibInit {initialize the cache library} {<b><i>cacheArchLibInit</i>\( \)</b>} {<b><i><a href="./cacheArchLib.html#cacheArchLibInit">cacheArchLibInit</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheArchClearEntry {clear an entry from a cache (68K, x86)} {<b><i>cacheArchClearEntry</i>\( \)</b>} {<b><i><a href="./cacheArchLib.html#cacheArchClearEntry">cacheArchClearEntry</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheStoreBufEnable {enable the store buffer (MC68060 only)} {<b><i>cacheStoreBufEnable</i>\( \)</b>} {<b><i><a href="./cacheArchLib.html#cacheStoreBufEnable">cacheStoreBufEnable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheStoreBufDisable {disable the store buffer (MC68060 only)} {<b><i>cacheStoreBufDisable</i>\( \)</b>} {<b><i><a href="./cacheArchLib.html#cacheStoreBufDisable">cacheStoreBufDisable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}mmuPro32LibInit {initialize module} {<b><i>mmuPro32LibInit</i>\( \)</b>} {<b><i><a href="./mmuPro32Lib.html#mmuPro32LibInit">mmuPro32LibInit</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumCr4Get {get contents of CR4 register} {<b><i>pentiumCr4Get</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumCr4Get">pentiumCr4Get</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumCr4Set {sets specified value to the CR4 register} {<b><i>pentiumCr4Set</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumCr4Set">pentiumCr4Set</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcStart {start both PMC0 and PMC1} {<b><i>pentiumPmcStart</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcStart">pentiumPmcStart</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcStop {stop both PMC0 and PMC1} {<b><i>pentiumPmcStop</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcStop">pentiumPmcStop</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcStop1 {stop PMC1} {<b><i>pentiumPmcStop1</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcStop1">pentiumPmcStop1</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcGet {get the contents of PMC0 and PMC1} {<b><i>pentiumPmcGet</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcGet">pentiumPmcGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcGet0 {get the contents of PMC0} {<b><i>pentiumPmcGet0</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcGet0">pentiumPmcGet0</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcGet1 {get the contents of PMC1} {<b><i>pentiumPmcGet1</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcGet1">pentiumPmcGet1</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcReset {reset both PMC0 and PMC1} {<b><i>pentiumPmcReset</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcReset">pentiumPmcReset</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcReset0 {reset PMC0} {<b><i>pentiumPmcReset0</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcReset0">pentiumPmcReset0</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcReset1 {reset PMC1} {<b><i>pentiumPmcReset1</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumPmcReset1">pentiumPmcReset1</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumTscGet64 {get 64Bit TSC (Timestamp Counter)} {<b><i>pentiumTscGet64</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumTscGet64">pentiumTscGet64</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumTscGet32 {get the lower half of the 64Bit TSC (Timestamp Counter)} {<b><i>pentiumTscGet32</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumTscGet32">pentiumTscGet32</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumTscReset {reset the TSC (Timestamp Counter)} {<b><i>pentiumTscReset</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumTscReset">pentiumTscReset</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMsrGet {get the contents of the specified MSR (Model Specific Register)} {<b><i>pentiumMsrGet</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumMsrGet">pentiumMsrGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMsrSet {set a value to the specified MSR (Model Specific Registers)} {<b><i>pentiumMsrSet</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumMsrSet">pentiumMsrSet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumTlbFlush {flush TLBs (Translation Lookaside Buffers)} {<b><i>pentiumTlbFlush</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumTlbFlush">pentiumTlbFlush</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumSerialize {execute a serializing instruction CPUID} {<b><i>pentiumSerialize</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumSerialize">pentiumSerialize</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumBts {execute atomic compare-and-exchange instruction to set a bit} {<b><i>pentiumBts</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumBts">pentiumBts</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumBtc {execute atomic compare-and-exchange instruction to clear a bit} {<b><i>pentiumBtc</i>\( \)</b>} {<b><i><a href="./pentiumALib.html#pentiumBtc">pentiumBtc</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMtrrEnable {enable MTRR (Memory Type Range Register)} {<b><i>pentiumMtrrEnable</i>\( \)</b>} {<b><i><a href="./pentiumLib.html#pentiumMtrrEnable">pentiumMtrrEnable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMtrrDisable {disable MTRR (Memory Type Range Register)} {<b><i>pentiumMtrrDisable</i>\( \)</b>} {<b><i><a href="./pentiumLib.html#pentiumMtrrDisable">pentiumMtrrDisable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMtrrGet {get MTRRs to a specified MTRR table} {<b><i>pentiumMtrrGet</i>\( \)</b>} {<b><i><a href="./pentiumLib.html#pentiumMtrrGet">pentiumMtrrGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMtrrSet {set MTRRs from specified MTRR table with WRMSR instruction.} {<b><i>pentiumMtrrSet</i>\( \)</b>} {<b><i><a href="./pentiumLib.html#pentiumMtrrSet">pentiumMtrrSet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumMcaShow {show MCA (Machine Check Architecture) registers } {<b><i>pentiumMcaShow</i>\( \)</b>} {<b><i><a href="./pentiumShow.html#pentiumMcaShow">pentiumMcaShow</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}pentiumPmcShow {show PMCs (Performance Monitoring Counters)} {<b><i>pentiumPmcShow</i>\( \)</b>} {<b><i><a href="./pentiumShow.html#pentiumPmcShow">pentiumPmcShow</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICDisable {disable the I960Jx instruction cache (i960)} {<b><i>cacheI960JxICDisable</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICDisable">cacheI960JxICDisable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICEnable {enable the I960Jx instruction cache (i960)} {<b><i>cacheI960JxICEnable</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICEnable">cacheI960JxICEnable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICInvalidate {invalidate the I960Jx instruction cache (i960)} {<b><i>cacheI960JxICInvalidate</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICInvalidate">cacheI960JxICInvalidate</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICLoadNLock {load and lock the I960Jx instruction cache (i960)} {<b><i>cacheI960JxICLoadNLock</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICLoadNLock">cacheI960JxICLoadNLock</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICStatusGet {get the I960Jx instruction cache status (i960)} {<b><i>cacheI960JxICStatusGet</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICStatusGet">cacheI960JxICStatusGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICLockingStatusGet {get the I960Jx I-cache locking status (i960)} {<b><i>cacheI960JxICLockingStatusGet</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICLockingStatusGet">cacheI960JxICLockingStatusGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxICFlush {flush the I960Jx instruction cache (i960)} {<b><i>cacheI960JxICFlush</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxICFlush">cacheI960JxICFlush</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxDCDisable {disable the I960Jx data cache (i960)} {<b><i>cacheI960JxDCDisable</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxDCDisable">cacheI960JxDCDisable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxDCEnable {enable the I960Jx data cache (i960)} {<b><i>cacheI960JxDCEnable</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxDCEnable">cacheI960JxDCEnable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxDCInvalidate {invalidate the I960Jx data cache (i960)} {<b><i>cacheI960JxDCInvalidate</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxDCInvalidate">cacheI960JxDCInvalidate</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxDCCoherent {ensure data cache coherency (i960)} {<b><i>cacheI960JxDCCoherent</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxDCCoherent">cacheI960JxDCCoherent</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxDCStatusGet {get the I960Jx data cache status (i960)} {<b><i>cacheI960JxDCStatusGet</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxDCStatusGet">cacheI960JxDCStatusGet</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxDCFlush {flush the I960Jx data cache (i960)} {<b><i>cacheI960JxDCFlush</i>\( \)</b>} {<b><i><a href="./cacheI960JxALib.html#cacheI960JxDCFlush">cacheI960JxDCFlush</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960JxLibInit {initialize the I960Jx cache library (i960)} {<b><i>cacheI960JxLibInit</i>\( \)</b>} {<b><i><a href="./cacheI960JxLib.html#cacheI960JxLibInit">cacheI960JxLibInit</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960CxICDisable {disable the I960Cx instruction cache (i960)} {<b><i>cacheI960CxICDisable</i>\( \)</b>} {<b><i><a href="./cacheI960CxALib.html#cacheI960CxICDisable">cacheI960CxICDisable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960CxICEnable {enable the I960Cx instruction cache (i960)} {<b><i>cacheI960CxICEnable</i>\( \)</b>} {<b><i><a href="./cacheI960CxALib.html#cacheI960CxICEnable">cacheI960CxICEnable</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960CxICInvalidate {invalidate the I960Cx instruction cache (i960)} {<b><i>cacheI960CxICInvalidate</i>\( \)</b>} {<b><i><a href="./cacheI960CxALib.html#cacheI960CxICInvalidate">cacheI960CxICInvalidate</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960CxICLoadNLock {load and lock I960Cx 512-byte instruction cache (i960)} {<b><i>cacheI960CxICLoadNLock</i>\( \)</b>} {<b><i><a href="./cacheI960CxALib.html#cacheI960CxICLoadNLock">cacheI960CxICLoadNLock</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}cacheI960CxIC1kLoadNLock {load and lock I960Cx 1KB instruction cache (i960)} {<b><i>cacheI960CxIC1kLoadNLock</i>\( \)</b>} {<b><i><a href="./cacheI960CxALib.html#cacheI960CxIC1kLoadNLock">cacheI960CxIC1kLoadNLock</a></i>(\ )</b>} {VxWorks Reference Manual} Libraries {} {}?? 快捷鍵說明
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