/*--------------------------------------------------------------------------
SST89x55x.H

Header file for 8-bit SST microcontrollers.
Copyright 2003 VCOM Technology Co,.Ltd.
All rights reserved.
--------------------------------------------------------------------------*/

/*  BYTE Registers  */
sfr P0    = 0x80;//Port 0.
sfr P1    = 0x90;//Port 1.
sfr P2    = 0xA0;//Port 2.
sfr P3    = 0xB0;//Port 3.
sfr PSW   = 0xD0;//Program Status Word.
sfr ACC   = 0xE0;//Accumulator.
sfr B     = 0xF0;//B Regester.
sfr SP    = 0x81;//Stack Pointer.
sfr DPL   = 0x82;//Data Pointer Low.
sfr DPH   = 0x83;//Data Pointer High.
sfr PCON  = 0x87;//Power Control.
sfr TCON  = 0x88;//Timer/Counter Control.
sfr TMOD  = 0x89;//Timer/Counter Mode Control.
sfr TL0   = 0x8A;//Timer 0 LSB.
sfr TL1   = 0x8B;//Timer 1 LSB.
sfr TH0   = 0x8C;//Timer 0 MSB.
sfr TH1   = 0x8D;//Timer 1 MSB.
sfr IE    = 0xA8;//Interrupt Enable.
sfr IP    = 0xB8;//Interrupt Priority Reg.
sfr SCON  = 0x98;//Serial Port Control.
sfr SBUF  = 0x99;//Serial Data Buffer.

/*  8052 Extensions  */
sfr T2CON  = 0xC8;//Timer/Counter 2 Contrl.
sfr T2MOD  = 0xC9;//Timer/Counter 2 Mode Contrl.
sfr RCAP2L = 0xCA;//Timer 2 Capture LSB
sfr RCAP2H = 0xCB;//Timer 2 Capture MSB.
sfr TL2    = 0xCC;//Timer 2 LSB.
sfr TH2    = 0xCD;//Timer 2 MSB.

/*  89x564 Extensions */
sfr WDTD  = 0x85;//Watchdog Data/Reload.
sfr WDTC  = 0xC0;//Watchdog Timer Control.
sfr SPDR  = 0x86;
sfr AUXR  = 0x8E;//Auxiliary Reg.
sfr AUXR1 = 0xA2;//Auxiliary Reg 1.
sfr SADDR = 0xA9;//Slave Address.
sfr SADEN = 0xB9;//Slave Address Mask.
sfr SPSR  = 0xAA;
sfr SFCF  = 0xB1;//SuperFlash Configuration.
sfr SFCM  = 0xB2;//SuperFlash Command.
sfr SFAL  = 0xB3;//SuperFlash Address Low.
sfr SFAH  = 0xB4;//SuperFlash Address HIgh.
sfr SFDT  = 0xB5;//SuperFlash Data.
sfr SFST  = 0xB6;//SuperFlash Status.
sfr SPCR  = 0xD5;
sfr CH    = 0xF9;//PCA Timer/Counter High.
sfr CL    = 0xE9;//PCA Timer/Counter Low.
sfr CCON  = 0xD8;//PCA Timer/Counter Control Register.
sfr CMOD  = 0xD9;//PCA Timer/Counter Mode Register.
sfr CCAPM0= 0xDA;//PCA Compare/Capture Module 0 Mode Register.
sfr CCAPM1= 0xDB;//PCA Compare/Capture Module 1 Mode Register.
sfr CCAPM2= 0xDC;//PCA Compare/Capture Module 2 Mode Register.
sfr CCAPM3= 0xDD;//PCA Compare/Capture Module 3 Mode Register.
sfr CCAPM4= 0xDE;//PCA Compare/Capture Module 4 Mode Register.
sfr CCAP0H= 0xFA;//PCA Module 0 Compare/Capture Register High.
sfr CCAP0L= 0xEA;//PCA Module 0 Compare/Capture Register Low.
sfr CCAP1H= 0xFB;//PCA Module 1 Compare/Capture Register High.
sfr CCAP1L= 0xEB;//PCA Module 1 Compare/Capture Register Low.
sfr CCAP2H= 0xFC;//PCA Module 2 Compare/Capture Register High.
sfr CCAP2L= 0xEC;//PCA Module 2 Compare/Capture Register Low.
sfr CCAP3H= 0xFD;//PCA Module 3 Compare/Capture Register High.
sfr CCAP3L= 0xED;//PCA Module 3 Compare/Capture Register Low.
sfr CCAP4H= 0xFE;//PCA Module 4 Compare/Capture Register High.
sfr CCAP4L= 0xEE;//PCA Module 4 Compare/Capture Register Low.

sfr IEA   = 0xE8;//Interrupt Enable A.
sfr IPA   = 0xF8;//Interrupt Priority Register A.
sfr IPAH  = 0xF7;//Interrupt Priority Register A High.
sfr IPH   = 0xB7;//Interrupt Priority Register High.

/*  BIT Registers  */
/*  PSW  */
sbit CY    = PSW^7;
sbit AC    = PSW^6;
sbit F0    = PSW^5;
sbit RS1   = PSW^4;
sbit RS0   = PSW^3;
sbit OV    = PSW^2;
sbit P     = PSW^0; //8052 only

/*  TCON  */
sbit TF1   = TCON^7;
sbit TR1   = TCON^6;
sbit TF0   = TCON^5;
sbit TR0   = TCON^4;
sbit IE1   = TCON^3;
sbit IT1   = TCON^2;
sbit IE0   = TCON^1;
sbit IT0   = TCON^0;

/*  IE  */
sbit EA    = IE^7;
sbit EC    = IE^6;
sbit ET2   = IE^5; //8052 only
sbit ES    = IE^4;
sbit ET1   = IE^3;
sbit EX1   = IE^2;
sbit ET0   = IE^1;
sbit EX0   = IE^0;

/*  IEA  */
sbit EBO   = IEA^3;

/*  IP  */
sbit PPC   = IP^6;
sbit PT2   = IP^5;
sbit PS    = IP^4;
sbit PT1   = IP^3;
sbit PX1   = IP^2;
sbit PT0   = IP^1;
sbit PX0   = IP^0;

/*  IPA  */
sbit PBO    = IPA^3;

/*  SCON  */
sbit SM0   = SCON^7;
sbit SM1   = SCON^6;
sbit SM2   = SCON^5;
sbit REN   = SCON^4;
sbit TB8   = SCON^3;
sbit RB8   = SCON^2;
sbit TI    = SCON^1;
sbit RI    = SCON^0;

/*  T2CON  */
sbit TF2    = T2CON^7;
sbit EXF2   = T2CON^6;
sbit RCLK   = T2CON^5;
sbit TCLK   = T2CON^4;
sbit EXEN2  = T2CON^3;
sbit TR2    = T2CON^2;
sbit C_T2   = T2CON^1;
sbit CP_RL2 = T2CON^0;

/*  CCON  */
sbit CF     = CCON^7;
sbit CR     = CCON^6;
sbit CCF4   = CCON^4;
sbit CCF3   = CCON^3;
sbit CCF2   = CCON^2;
sbit CCF1   = CCON^1;
sbit CCF0   = CCON^0;

/*  B  */
sbit B7     = B^7;
sbit B6     = B^6;
sbit B5     = B^5;
sbit B4     = B^4;
sbit B3     = B^3;
sbit B2     = B^2;
sbit B1     = B^1;
sbit B0     = B^0;

/*  ACC  */
sbit ACC7   = ACC^7;
sbit ACC6   = ACC^6;
sbit ACC5   = ACC^5;
sbit ACC4   = ACC^4;
sbit ACC3   = ACC^3;
sbit ACC2   = ACC^2;
sbit ACC1   = ACC^1;
sbit ACC0   = ACC^0;

/*  WDTC  */
sbit WDOUT  = WDTC^4;
sbit WDRE   = WDTC^3;
sbit WDTS   = WDTC^2;
sbit WDT    = WDTC^1;
sbit SWDT   = WDTC^0;

/*  P1  */
sbit P17=P1^7;
sbit P16=P1^6;
sbit P15=P1^5;
sbit P14=P1^4;
sbit P13=P1^3;
sbit P12=P1^2;
sbit P11=P1^1;
sbit P10=P1^0;

/*  P1  */
sbit T2EX  = P1^1; // 8052 only
sbit T2    = P1^0; // 8052 only

/*  P2  */
sbit P27=P2^7;
sbit P26=P2^6;
sbit P25=P2^5;
sbit P24=P2^4;
sbit P23=P2^3;
sbit P22=P2^2;
sbit P21=P2^1;
sbit P20=P2^0;

/*  P3  */
sbit P37=P3^7;
sbit P36=P3^6;
sbit P35=P3^5;
sbit P34=P3^4;
sbit P33=P3^3;
sbit P32=P3^2;
sbit P31=P3^1;
sbit P30=P3^0;

/*  P3  */
sbit RD    = P3^7;
sbit WR    = P3^6;
sbit T1    = P3^5;
sbit T0    = P3^4;
sbit INT1  = P3^3;
sbit INT0  = P3^2;
sbit TXD   = P3^1;
sbit RXD   = P3^0;