?? dtmf2.lss
字號:
dtmf2.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000616 00000000 00000000 00000094 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000000 00800060 00000616 000006aa 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 0000001a 00800060 00800060 000006aa 2**0
ALLOC
3 .noinit 00000000 0080007a 0080007a 000006aa 2**0
CONTENTS
4 .eeprom 00000000 00810000 00810000 000006aa 2**0
CONTENTS
5 .stab 00001014 00000000 00000000 000006ac 2**2
CONTENTS, READONLY, DEBUGGING
6 .stabstr 000009fb 00000000 00000000 000016c0 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 1b c0 rjmp .+54 ; 0x38
2: 33 c0 rjmp .+102 ; 0x6a
4: 95 c0 rjmp .+298 ; 0x130
6: 31 c0 rjmp .+98 ; 0x6a
8: 30 c0 rjmp .+96 ; 0x6a
a: 2f c0 rjmp .+94 ; 0x6a
c: c5 c0 rjmp .+394 ; 0x198
e: 2d c0 rjmp .+90 ; 0x6a
10: 2c c0 rjmp .+88 ; 0x6a
12: 2b c0 rjmp .+86 ; 0x6a
14: 2a c0 rjmp .+84 ; 0x6a
00000016 <__ctors_end>:
16: 44 54 subi r20, 0x44 ; 68
18: 4d 46 sbci r20, 0x6D ; 109
1a: 20 44 sbci r18, 0x40 ; 64
1c: 65 63 ori r22, 0x35 ; 53
1e: 6f 64 ori r22, 0x4F ; 79
20: 65 72 andi r22, 0x25 ; 37
22: 20 62 ori r18, 0x20 ; 32
24: 79 20 and r7, r9
26: 77 77 andi r23, 0x77 ; 119
28: 77 2e mov r7, r23
2a: 69 6e ori r22, 0xE9 ; 233
2c: 66 69 ori r22, 0x96 ; 150
2e: 64 69 ori r22, 0x94 ; 148
30: 67 6d ori r22, 0xD7 ; 215
32: 2e 6e ori r18, 0xEE ; 238
34: 65 74 andi r22, 0x45 ; 69
...
00000038 <__init>:
38: 11 24 eor r1, r1
3a: 1f be out 0x3f, r1 ; 63
3c: cf ed ldi r28, 0xDF ; 223
3e: cd bf out 0x3d, r28 ; 61
00000040 <__do_copy_data>:
40: 10 e0 ldi r17, 0x00 ; 0
42: a0 e6 ldi r26, 0x60 ; 96
44: b0 e0 ldi r27, 0x00 ; 0
46: e6 e1 ldi r30, 0x16 ; 22
48: f6 e0 ldi r31, 0x06 ; 6
4a: 03 c0 rjmp .+6 ; 0x52
0000004c <.do_copy_data_loop>:
4c: c8 95 lpm
4e: 31 96 adiw r30, 0x01 ; 1
50: 0d 92 st X+, r0
00000052 <.do_copy_data_start>:
52: a0 36 cpi r26, 0x60 ; 96
54: b1 07 cpc r27, r17
56: d1 f7 brne .-12 ; 0x4c
00000058 <__do_clear_bss>:
58: 10 e0 ldi r17, 0x00 ; 0
5a: a0 e6 ldi r26, 0x60 ; 96
5c: b0 e0 ldi r27, 0x00 ; 0
5e: 01 c0 rjmp .+2 ; 0x62
00000060 <.do_clear_bss_loop>:
60: 1d 92 st X+, r1
00000062 <.do_clear_bss_start>:
62: aa 37 cpi r26, 0x7A ; 122
64: b1 07 cpc r27, r17
66: e1 f7 brne .-8 ; 0x60
68: 01 c0 rjmp .+2 ; 0x6c
0000006a <__bad_interrupt>:
6a: ca cf rjmp .-108 ; 0x0
0000006c <main>:
volatile unsigned char up; //up flag
volatile unsigned char dn; //down flag
int main (void)
{
6c: cf ed ldi r28, 0xDF ; 223
6e: d0 e0 ldi r29, 0x00 ; 0
70: de bf out 0x3e, r29 ; 62
72: cd bf out 0x3d, r28 ; 61
cli();
74: f8 94 cli
//Setup Ports
DDRB = 0x00; //Set PORTB as input
76: 17 ba out 0x17, r1 ; 23
DDRD = 0x70; //Set PORTD output pins
78: 80 e7 ldi r24, 0x70 ; 112
7a: 81 bb out 0x11, r24 ; 17
cbi(PORTB,4); //HiZ - Disable decoder chip's output
7c: c4 98 cbi 0x18, 4 ; 24
//Setup UATRT
UBRR = (char)UART_BAUD_SELECT;
7e: 86 e1 ldi r24, 0x16 ; 22
80: 89 b9 out 0x09, r24 ; 9
UCR = 0x08; //enable Tx
82: 88 e0 ldi r24, 0x08 ; 8
84: 8a b9 out 0x0a, r24 ; 10
//Setup TimerCounter0
TCCR0 = 0x03; //Set TC0 to ck/64 4.5mS IRQs
86: 83 e0 ldi r24, 0x03 ; 3
88: 83 bf out 0x33, r24 ; 51
TIMSK = 0x02; //Enable OV0 INT
8a: 82 e0 ldi r24, 0x02 ; 2
8c: 89 bf out 0x39, r24 ; 57
//Setup MCU
GIMSK = 0x80; //Enable INT1
8e: 80 e8 ldi r24, 0x80 ; 128
90: 8b bf out 0x3b, r24 ; 59
MCUCR = 0x2C; //Setup Sleep mode & INT1 rising
92: 8c e2 ldi r24, 0x2C ; 44
94: 85 bf out 0x35, r24 ; 53
GIFR = 0xC0; //Clear INT1 Flag
96: 80 ec ldi r24, 0xC0 ; 192
98: 8a bf out 0x3a, r24 ; 58
for(eepos=0;eepos<255;eepos++) { //scan eeprom for marker byte
9a: 10 92 64 00 sts 0x0064, r1
if(eread(eepos)==0x0F) break;
9e: 80 91 64 00 lds r24, 0x0064
a2: 70 d1 rcall .+736 ; 0x384
a4: 8f 30 cpi r24, 0x0F ; 15
a6: 39 f0 breq .+14 ; 0xb6
a8: 80 91 64 00 lds r24, 0x0064
ac: 8f 5f subi r24, 0xFF ; 255
ae: 80 93 64 00 sts 0x0064, r24
b2: 8f 3f cpi r24, 0xFF ; 255
b4: a1 f7 brne .-24 ; 0x9e
}
eref = eepos; //set end of line 18 at end of eeprom
b6: 80 91 64 00 lds r24, 0x0064
ba: 80 93 78 00 sts 0x0078, r24
lcdln = 19;
be: 83 e1 ldi r24, 0x13 ; 19
c0: 80 93 62 00 sts 0x0062, r24
redraw = 1; //Redraw incoming screen on first digit recieved
c4: 81 e0 ldi r24, 0x01 ; 1
c6: 80 93 73 00 sts 0x0073, r24
lcdcmd (0x01); //Clear LCD, move home
ca: 68 2f mov r22, r24
cc: 80 e0 ldi r24, 0x00 ; 0
ce: 55 d2 rcall .+1194 ; 0x57a
lcdcmd (0x02); //Home Cursor
d0: 62 e0 ldi r22, 0x02 ; 2
d2: 80 e0 ldi r24, 0x00 ; 0
d4: 52 d2 rcall .+1188 ; 0x57a
lcdcmd (0x38); //Set 8-bit interface
d6: 68 e3 ldi r22, 0x38 ; 56
d8: 80 e0 ldi r24, 0x00 ; 0
da: 4f d2 rcall .+1182 ; 0x57a
lcdcmd (0x0C); //No cursor, display visable
dc: 6c e0 ldi r22, 0x0C ; 12
de: 80 e0 ldi r24, 0x00 ; 0
e0: 4c d2 rcall .+1176 ; 0x57a
lcdcmd (0x06); //Incement display address
e2: 66 e0 ldi r22, 0x06 ; 6
e4: 80 e0 ldi r24, 0x00 ; 0
e6: 49 d2 rcall .+1170 ; 0x57a
TXbyte ('\r');
e8: 8d e0 ldi r24, 0x0D ; 13
ea: 3b d1 rcall .+630 ; 0x362
TXbyte ('\n');
ec: 8a e0 ldi r24, 0x0A ; 10
ee: 39 d1 rcall .+626 ; 0x362
PRINT ("DTMF Decoder by www.infidigm.net"); //build message on lcd and out uart
f0: 86 e1 ldi r24, 0x16 ; 22
f2: 90 e0 ldi r25, 0x00 ; 0
f4: 0a d1 rcall .+532 ; 0x30a
TXbyte ('\r');
f6: 8d e0 ldi r24, 0x0D ; 13
f8: 34 d1 rcall .+616 ; 0x362
TXbyte ('\n');
fa: 8a e0 ldi r24, 0x0A ; 10
fc: 32 d1 rcall .+612 ; 0x362
for (a=0;a<255;a++) {
fe: 10 92 79 00 sts 0x0079, r1
TXbyte(fltr(eread(a + eepos+1))); //Send entire eeprom out the UART
102: 80 91 79 00 lds r24, 0x0079
106: 90 91 64 00 lds r25, 0x0064
10a: 89 0f add r24, r25
10c: 8f 5f subi r24, 0xFF ; 255
10e: 3a d1 rcall .+628 ; 0x384
110: 1c d2 rcall .+1080 ; 0x54a
112: 27 d1 rcall .+590 ; 0x362
114: 80 91 79 00 lds r24, 0x0079
118: 8f 5f subi r24, 0xFF ; 255
11a: 80 93 79 00 sts 0x0079, r24
11e: 8f 3f cpi r24, 0xFF ; 255
120: 81 f7 brne .-32 ; 0x102
}
TXbyte ('\r');
122: 8d e0 ldi r24, 0x0D ; 13
124: 1e d1 rcall .+572 ; 0x362
TXbyte ('\n');
126: 8a e0 ldi r24, 0x0A ; 10
128: 1c d1 rcall .+568 ; 0x362
sei();
12a: 78 94 sei
for(;;) sleep(); //idle until Interrupt
12c: 88 95 sleep
12e: fe cf rjmp .-4 ; 0x12c
00000130 <__vector_2>:
}
SIGNAL(SIG_INTERRUPT1) //Exturnal IRQ from DTMF decoder handler
{
130: 1f 92 push r1
132: 0f 92 push r0
134: 0f b6 in r0, 0x3f ; 63
136: 0f 92 push r0
138: 11 24 eor r1, r1
13a: 1f 93 push r17
13c: 2f 93 push r18
13e: 3f 93 push r19
140: 4f 93 push r20
142: 5f 93 push r21
144: 6f 93 push r22
146: 7f 93 push r23
148: 8f 93 push r24
14a: 9f 93 push r25
14c: af 93 push r26
14e: bf 93 push r27
150: ef 93 push r30
152: ff 93 push r31
unsigned char digit;
cli();
154: f8 94 cli
DDRB = 0x00; //Set PORTB = input
156: 17 ba out 0x17, r1 ; 23
sbi(PORTD,4); //Enable decoder chip's output
158: 94 9a sbi 0x12, 4 ; 18
nop();
15a: 00 00 nop
digit = PINB; //read dtmf digit
15c: 16 b3 in r17, 0x16 ; 22
cbi(PORTD,4); //HiZ - Disable decoder chip's output
15e: 94 98 cbi 0x12, 4 ; 18
digit=digit&0x0F; //Stip off top 4 bits
160: 1f 70 andi r17, 0x0F ; 15
updtlcd(fltr(digit)); //send digit to LCD
162: 81 2f mov r24, r17
164: f2 d1 rcall .+996 ; 0x54a
166: 6d d1 rcall .+730 ; 0x442
store(digit); //write digit to eeprom
168: 81 2f mov r24, r17
16a: 1d d1 rcall .+570 ; 0x3a6
TXbyte(fltr(digit)); //send digit out the UART
16c: 81 2f mov r24, r17
16e: ed d1 rcall .+986 ; 0x54a
170: f8 d0 rcall .+496 ; 0x362
sei();
172: 78 94 sei
}
174: ff 91 pop r31
176: ef 91 pop r30
178: bf 91 pop r27
17a: af 91 pop r26
17c: 9f 91 pop r25
17e: 8f 91 pop r24
180: 7f 91 pop r23
182: 6f 91 pop r22
184: 5f 91 pop r21
186: 4f 91 pop r20
188: 3f 91 pop r19
18a: 2f 91 pop r18
18c: 1f 91 pop r17
18e: 0f 90 pop r0
190: 0f be out 0x3f, r0 ; 63
192: 0f 90 pop r0
194: 1f 90 pop r1
196: 18 95 reti
00000198 <__vector_6>:
SIGNAL(SIG_OVERFLOW0) //TC0 overflow IRQ handle - every 4.5mS
{
198: 1f 92 push r1
19a: 0f 92 push r0
19c: 0f b6 in r0, 0x3f ; 63
19e: 0f 92 push r0
1a0: 11 24 eor r1, r1
1a2: 1f 93 push r17
1a4: 2f 93 push r18
1a6: 3f 93 push r19
1a8: 4f 93 push r20
1aa: 5f 93 push r21
1ac: 6f 93 push r22
1ae: 7f 93 push r23
1b0: 8f 93 push r24
1b2: 9f 93 push r25
1b4: af 93 push r26
1b6: bf 93 push r27
1b8: cf 93 push r28
1ba: ef 93 push r30
1bc: ff 93 push r31
if((PIND >> PD0) & 1) { //test if up button is released
1be: 80 9b sbis 0x10, 0 ; 16
1c0: 0e c0 rjmp .+28 ; 0x1de
uptimeL=22; //reset up depressed timer
1c2: 86 e1 ldi r24, 0x16 ; 22
1c4: 80 93 74 00 sts 0x0074, r24
if(uptimeH<22)uptimeH++; //increment up released timer
1c8: 80 91 76 00 lds r24, 0x0076
1cc: 86 31 cpi r24, 0x16 ; 22
1ce: 20 f4 brcc .+8 ; 0x1d8
1d0: 8f 5f subi r24, 0xFF ; 255
1d2: 80 93 76 00 sts 0x0076, r24
1d6: 41 c0 rjmp .+130 ; 0x25a
else up=0; //indicate up filtered release
1d8: 10 92 61 00 sts 0x0061, r1
1dc: 3e c0 rjmp .+124 ; 0x25a
}
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