'\" t.so wrs.an.\" iq80310/target.nr - target-specific documentation.\".\" Copyright 1999-2001 Wind River Systems, Inc..\".\" modification history.\" --------------------.\" 01a,08jul02,scm  document INCLUDE_HSI_PROBE....\" 01a,21jun02,scm  add bspVal comments.\" 01b,24aug01,dgp  change manual entry to reference entry per SPR 23698.\" 01a,26Apr01,rec  created, derived from integrator940t.\".TH iq80310 T "Intel iq80310" "Rev: 01 May 00" "TORNADO REFERENCE: VXWORKS".SH "NAME".aX "Intel iq80310".SH "INTRODUCTION"This reference entry provides board-specific information necessary to runVxWorks for the iq80310 BSP.  The iq80310 BSP release requires anIntel iq80310 development board.  This is the only board currently supportedby the BSP. Before running vxWorks, verify that the board runs in thefactory configuration.The iq80310 BSP is based around the Intel 80310 I/O Processor chipset.  Thisset is composed of the Intel 80200 processor (XScale) and the Intel 80312I/O companion chip.The iq80310 BSP/development board supports flexible expansion:.IPAuto configurable DRAM from 32 MB to 512 MB..IPPCI bus bridge allowing PCI expansion cards to be mounted..IPOperation as a PCI bus master in a passive backplane, or as a slavein a PC system..LP.SS "iq80310 BSP DETAILS".SS "Boot ROMs"The default boot image provided with this BSP includes amechanism for loading a standard VxWorks image.The boot ROM image has been tested running from flash.When building bootroms under diab be sure to uncomment the lines in the Makefilewhich include "-kill-opt=0x10000 -Xkill-reorder=8". There are currently someoptimization issues using the diab compiler.The Intel Flash Recovery Utility (FRU) can be used to program the imageinto flash.  For this, the boot ROM needs to be generated and convertedto binary format:.CS   make bootrom.CEThis build generates the file, 'bootrom.bin', that is thendownloaded to the board via the Intel supplied FRU program.The board uses the new image to boot and loads the VxWorks imagesdeveloped from the BSP. Refer to the.I "Intel iq80310 Evaluation Platform Manual,appendix D, iq8310 Board Flash Programming", for more information on using the FRU..SS "visionWARE Considerations"To program on board Boot Flash via visionClick: (1) create bootrom.hex, then ..\estii\convert bootrom.hex -a -l 0 -u 800000, (this     will create a bootrom.bin compatible with visionClick...) (2) bring up vClick, activate your project, then issue the command :     SR FEBR1 FE000000 (3) under Tools, Program Flash Devices, select the following options:Image:                 point to your bootrom.bin imageProgramming Algorithm: INTEL 28F640Jx (8192 x 8) 1 DeviceBias:                  0xFE000000Base Address:          0xFE000000 (check erase all)Erase to:              0x007FFFFFStart Address:         0xA0000000Bytes of Target RAM:   16000Select "Erase Only", on completion select "Program Only".NOTE: If an error message () is seen while erasing the flash, please verify that your flash       is receiving the correct voltages for erase/program. If there is a voltage issue with the       backplane it could be causing a failure. The most likely scenario would be the PCI backplane       not being 100% compatible with supply voltages (for example no +-12V) required by the flash.      Some customers have experienced little issues with programming the flash and other can not. A      12 volt back plane should be used.To use your image with visionCLICK and visionPROBE II, you must use thevisionWARE provided utilities to create visionWARE-compliant bootrom.binand vxWorks.bdx images.The new 'bootrom' file must be converted to the proper format using theinstructions provided in 'Creating the proper vxWorks.bdx, bootrom.bdx,and bootrom.bin to run under visionWARE' below.  Once converted, usevisionPROBE II or visionICE II  to program the image to flash..SS "Creating the proper vxWorks.bdx, bootrom.bdx, and bootrom.bin to run under visionWARE"In order to use visionClick/visionProbe, you must convert the standard bootROM and VxWorks images generated via the makefile to the proper format forvisionWARE. To generate the proper format, complete the following steps:.IP "1)"Under your local 'estii' directory run the 'objcvt' utility on your VxWorksimage to produce a vxWorks.bdx image for visionWARE.( <command prompt> ..\..\estii\objcvt vxWorks ).IP "2)"Under your local 'estii' directory run the 'objcvt' utility on your bootROM image to produce a bootrom.bdx image for visionWARE.( <command prompt> ..\..\estii\objcvt bootrom ).IP "3)"Under your local 'estii' directory run the 'convert' utility on yourbootrom.hex image to produce a bootrom.bin image for visionWARE.( <command prompt> ..\..\estii\convert bootrom.hex -a -l 0 -u 800000 )Example, To build a standalone vxWorks image to run under visionClick/Probe,modify config.h to:  (1) re-define "INCLUDE_HSI_PROBE",  (2) re-define "STANDALONE_NET",  (3) modify DEFAULT_BOOT_LINE, so, h="host ip", e="boards ip", and tn="name foe target"  (4) undefine "INCLUDE_FLASH"in BSP directory perform "make vxWorks.st"under visionClick/Probe you must convert your vxWorks.st into a "bdx" image... select from menu bar: " TOOLS/CONVERT OBJECT MODULES", and   (1) add path to vxWorks.st image,   (2) check "create symbol file for visionClick"   (3) check "create bdx file for RAM download"  (command at bottom of this window after the above selections should look something like:     D:\ESTII\convert.exe "Z:\wpwr\target\config\iq80310\vxWorks.st" -c -m gnu -b -z).SS "Libraries"This BSP release requires three directories which contain objectfiles for the XScale microarchitecture:.CS    objXSCALEgnuvx    objXSCALEgnuvxwv    objXSCALEgnutest.CEThese object files are built into the following architecture libraries:.CS    target/lib/libXSCALEgnuvx.a    target/lib/libXSCALEgnuwv.a    target/lib/libXSCALEgnugcc.a    target/lib/libXSCALEgnutest.a.CEThese files, along with the BSP, are used to construct a VxWorks imagedesigned to run on the iq80310 development board.  Please refer to the.I "Tornado BSP Developer's Kit for VxWorks User's Guide"for more information on building the various VxWorks images..SS "Flash memory as NVRAM"If the BSP is configured with INCLUDE_FLASH defined, standard VxWorksflash support is included.The following information may be required (depending on your boot method) forstorage in flash:	boot device	unit number	processor number	host name	file name	inet on ethernet (e)	host inet (h)	gateway inet (g)	user (u)	ftp password (pw)	flags (f)	target name (tn)Please refer to the.I "Tornado User's Guide"for more information on booting VxWorks..SS "SDRAM"The iq80310 development board is equipped with a 168-pin DIMM socketformatted to accept +3.3 V synchronous DRAM with Error Correction Code(ECC).  The socket will accept between 32 MB and 512 MB. The BSP is setup to auto-size memory and has been tested with 32, 64, 128, 256, and512 MB DIMMs..SS "Interrupts"The iq80312 companion chip has four external interrupts XINT0, XINT1, XINT2,and XINT3.  These interrupts have two internal sources of multiplexedinterrupts (XINT6 and XINT7).  For this BSP, there are a total of 8 levelsof interrupts (XIN0-XINT7) and each interrupt can be multiplexed up to32 levels.  XINT4 and XINT5 are reserved.Interrupt connections, enabling, and disabling are performed using thestandard intArchLib routines.  The interrupt controller driver isprovided in i80312IntrCtl.c..SS "Serial Configuration"There are two serial ports on the iq80310 development board.The default configuration is 9600 baud, 8 data bits, no parity, 1 stopbit.  The console serial ports are based on the 16C550 UART. COM1 isassociated with the J9 connector and COM2 is associated with the J10connector.  COM2 is used by the boot ROM and VxWorks image while COM1is used for user debug.  The maximum baud rate is 115200..SS "SCSI Configuration"The iq80310 development board does not have any on-card SCSI devices.This BSP does not support SCSI..SS "Network Configuration"The iq80310 development board provides a high speed Ethernet debug port.The Ethernet device supported is an Intel 82559ER Integrated PCIMAC/PHY device..SS "VME Access"The iq80310 development board does not have VME bus support..SS "PCI Access"Two PCI expansion slots are available on the iq80310 development board.  Theboard supports 64-bit, +3.3 V, 33MHz, or 66MHz PCI expansion.  The secondaryPCI bus speed is controlled via switch 2 on S1.  This BSP supports both PCIslots and has been tested with network expansion cards.The iq80310 BSP supports, and has been tested with, PCI Ethernet cardscontaining the Intel 82557 Ethernet network device.  This is a fast EthernetPCI bus controller, IEEE 802.3 10Base-T and 100Base-T compatible.  It alsofeatures a glueless 32-bit PCI bus master interface, fully compliant withPCI Spec version 2.1.  An interface to MII compliant physical layer devicesis built into the card..SH "SPECIAL CONSIDERATIONS".SS "Cache/MMU considerations"The iq80310 extends the page attributes defined by the C & B bits inthe page descriptors with an additional X bit. This bit allows additionalattributes to be encoded when X=1. To gain access to the X bit the iq80310BSP has been modified to support Extended Small Page Tables. The X bit isthe LSB of the TEX (type extension) field.If the X bit for a descriptor is zero, the C & B bits operate as mandatedby the ARM architecture. It the X bit for a descriptor is one, the C & Bbits meanings are extended.With this support the following state flags have been added:VM_STATE_CACHEABLE_MINICACHE - cache policy is determined by MD field                               of Auxiliary Control registerVM_STATE_EX_CACHEABLE        - write back, read/write allocateVM_STATE_EX_CACHEABLE_NOTVM_STATE_MASK_EX_CACHEABLEVM_STATE_EX_BUFFERABLE       - writes will not coalesce into buffersVM_STATE_EX_BUFFERABLE_NOTVM_STATE_MASK_EX_BUFFERABLEWith the state VM_STATE_CACHEABLE_MINICACHE set, pages set to this stateusing vmStateSet() will result in those pages being cached in themini-cache, and not in the main data cache.Calling cacheInvalidate(DATA_CACHE, ENTIRE_CACHE) will also invalidate themini-cache, but in all other aspects, no support is provided forthe mini-cache, and the user is entirely responsible for ensuringcache coherency.