/* i80312Pci.h - i80312 PCI header file *//* Copyright 2000 Wind River Systems, Inc. *//*modification history--------------------01g,23may01,scm  removed unused code01f,10may01,scm  add detection of PCI cards in backplane01e,14feb01,jb  Modifying PCI Init sequence01d,16jan01,jb  Adding Auto PCI Init01c,08dec00,jb  Adjusting ATU structure01b,06dec00,jb  Removing dependencies on sysEeprom.h01a,10oct00,jb   created from i960rp.*/#ifndef __INCi80312Pcih#define __INCi80312Pcih#ifdef __cplusplusextern "C" {#endif#ifndef _ASMLANGUAGE#define  U32P_CAST    (volatile UINT32 *)#define  U24P_CAST	(volatile UINT8 *)#define  U16P_CAST    (volatile UINT16 *)#define  U8P_CAST     (volatile UINT8 *)#else#define  U32P_CAST#define  U24P_CAST#define  U16P_CAST#define  U8P_CAST#endif#define PCI_MAX_DEV 8#define PCI_IO_ADR	0#define PCI_MEM_ADR	0#define PCI_INT_LVL	0#define PCI_INT_VEC	0#define PCI2DRAM_BASE_ADRS 0xa0000000/* Standard device configuration register offsets */#define	PCI_CFG_VENDOR_ID	0x00#define	PCI_CFG_DEVICE_ID	0x02#define	PCI_CFG_COMMAND		0x04#define	PCI_CFG_STATUS		0x06#define	PCI_CFG_REVISION	0x08#define	PCI_CFG_PROGRAMMING_IF	0x09#define	PCI_CFG_SUBCLASS	0x0a#define	PCI_CFG_CLASS		0x0b#define	PCI_CFG_CACHE_LINE_SIZE	0x0c#define	PCI_CFG_LATENCY_TIMER	0x0d#define	PCI_CFG_HEADER_TYPE	0x0e#define	PCI_CFG_BIST		0x0f#define	PCI_CFG_BASE_ADDRESS_0	0x10#define	PCI_CFG_BASE_ADDRESS_1	0x14#define	PCI_CFG_BASE_ADDRESS_2	0x18#define	PCI_CFG_BASE_ADDRESS_3	0x1c#define	PCI_CFG_BASE_ADDRESS_4	0x20#define	PCI_CFG_BASE_ADDRESS_5	0x24#define	PCI_CFG_BASE_RESERVED_6	0x28#define	PCI_CFG_BASE_RESERVED_7	0x2c#define	PCI_CFG_EXPANSION_ROM	0x30#define	PCI_CFG_RESERVED_34	0x34#define	PCI_CFG_RESERVED_38	0x38#define	PCI_CFG_INTERRUPT_LINE	0x3c#define	PCI_CFG_INTERRUPT_PIN	0x3d#define	PCI_CFG_MIN_GRANT	0x3e#define	PCI_CFG_MAX_LATENCY	0x3f#define PCI_CFG_DEV_INT_LINE	0x3c/* PCI-to-PCI bridge configuration register offsets */#define PCI_CFG_PRIMARY_BUS     0x18#define PCI_CFG_SECONDARY_BUS   0x19#define PCI_CFG_SUBORDINATE_BUS 0x1a#define PCI_CFG_SEC_LATENCY     0x1b#define PCI_CFG_IO_BASE         0x1c#define PCI_CFG_IO_LIMIT        0x1d#define PCI_CFG_SEC_STATUS      0x1e#define PCI_CFG_MEM_BASE        0x20#define PCI_CFG_MEM_LIMIT       0x22#define PCI_CFG_PRE_MEM_BASE    0x24#define PCI_CFG_PRE_MEM_LIMIT   0x26#define PCI_CFG_PRE_MEM_BASE_U  0x28#define PCI_CFG_PRE_MEM_LIMIT_U 0x2c#define PCI_CFG_IO_BASE_U       0x30#define PCI_CFG_IO_LIMIT_U      0x32#define PCI_CFG_ROM_BASE        0x38#define PCI_CFG_BRG_INT_LINE    0x3c#define PCI_CFG_BRG_INT_PIN     0x3d#define PCI_CFG_BRIDGE_CONTROL  0x3e#define PCI_CFG_SPECIAL_USE	0x41#define PCI_CFG_MODE		0x43/* multi function bit in header type field of config header */#define PCI_MULTI_FUNCTION       0x80  /*    0x00800000 *//* Command register values */#define PCI_CMD_IOSPACE                 (1 << 0)#define PCI_CMD_MEMSPACE                (1 << 1)#define PCI_CMD_BUS_MASTER              (1 << 2)#define PCI_CMD_SPECIAL                 (1 << 3)#define PCI_CMD_MWI_ENAB                (1 << 4)#define PCI_CMD_VGA_SNOOP               (1 << 5)#define PCI_CMD_PARITY                  (1 << 6)#define PCI_CMD_WAIT_CYC                (1 << 7)#define PCI_CMD_SERR_ENAB               (1 << 8)#define PCI_CMD_FBB_ENAB                (1 << 9)#define IO_SPACE_ENABLE                 0x0001#define MEM_SPACE_ENABLE                0x0002#define BUS_MASTER_ENABLE               0x0004#define SPECIAL_CYCLE_ENABLE            0x0008#define MWI_ENABLE                      0x0010#define VGA_SNOOP_ENABLE                0x0020#define PARITY_CHECK_ENABLE             0x0040#define WAIT_CYCLE_CONTROL              0x0080#define PSERR_ENABLE                    0x0100#define FAST_BACK_TO_BACK_ENABLE        0x0200/* Command extentions for power mgmt */#define SNOOZE_MODE			0x0040#define SLEEP_MODE_DIS			0x0000/* Status register values */#define PCI_66_MHZ_CAPABLE              0x0020#define UDF_SUPPORTED                   0x0040#define FAST_BACK_TO_BACK               0x0080#define MASTER_PARITY_ERROR             0x0100#define DEVSEL_TIMING                   0x0600#define TARGET_ABORT                    0x0800#define MASTER_TARGET_ABORT             0x1000#define MASTER_ABORT                    0x2000#define PSERR_ASSERTED                  0x4000#define PARITY_ERROR                    0x8000#define PIABR_PREFETCH                  0x8/* Expansion ROM defines */#define ROM_DECODE_ENABLE               0x1#define ROM_DECODE_DISABLE              0x0/* * Type 0 Pci Header. Applies to all pci devices * except bridges. */typedef struct   {   UINT16 vendorId;   UINT16 deviceId;   UINT16 command;   UINT16 status;   UINT8  revisionId;   UINT8  progIf;   UINT8  subClass;   UINT8  baseClass;   UINT8  cacheLineSize;   UINT8  latTimer;   UINT8  headerType;   UINT8  bist;   UINT32 baseMmRegs;   UINT32 baseImRegs;   UINT32 baseLocal;   UINT32 reserved1[5];   UINT32 baseExpRom;   UINT32 reserved2[2];   UINT8  intLine;   UINT8  intPin;   UINT8  minGnt;   UINT8  maxLat;   } PCI_CFG_SPACE;typedef struct   {    UINT16	PCI_Vendor_Id;				/* 0x00 */    UINT16	PCI_Device_Id;				/* 0x02 */    UINT16	PCI_PrimaryCommand;			/* 0x04 */    UINT16	PCI_PrimaryStatus;			/* 0x06 */    UINT8	PCI_Revision_ID;			/* 0x08 */    UINT8	PCI_progIf;				/* 0x09 */    UINT8	PCI_subClass;				/* 0x0A */    UINT8	PCI_baseClass;				/* 0x0B */    UINT8	PCI_Cacheline_Size;			/* 0x0C */    UINT8	PCI_Primary_Latency_Time;		/* 0x0D */    UINT8	PCI_Header_Type;			/* 0x0E */    UINT8	PCI_bist;				/* 0x0F */    UINT32	PCI_BaseAddress[2];			/* 0x10 */    UINT8	PCI_Primary_Bus_Number;			/* 0x18 */    UINT8	PCI_Secondary_Bus_Number;		/* 0x19 */    UINT8	PCI_Subordinate_Bus_Number;		/* 0x1A */    UINT8	PCI_Secondary_Latency_Timer;		/* 0x1B */    UINT8	PCI_Io_Base;				/* 0x1C */    UINT8	PCI_Io_Limit;				/* 0x1D */    UINT16	PCI_Secondary_Status;			/* 0x1E */    UINT16	PCI_Memory_Base;			/* 0x20 */    UINT16	PCI_Memory_Limit;			/* 0x22 */    UINT16	PCI_Prefetchable_Memory_Base;		/* 0x24 */    UINT16	PCI_Prefetchable_Memory_Limit;		/* 0x26 */    UINT32	PCI_Prefetchable_Base_Upper;		/* 0x28 */    UINT32	PCI_Prefetchable_Limit_Upper;		/* 0x2C */    UINT16	PCI_Io_Base_Upper;			/* 0x30 */    UINT16	PCI_Io_Limit_Upper;			/* 0x32 */    UINT32	PCI_reserved;				/* 0x34 */    UINT32	PCI_Expansion_ROM_Base_Address;		/* 0x38 */    UINT8	PCI_Interrupt_Line;			/* 0x3C */    UINT8	PCI_Interrupt_Pin;			/* 0x3D */    UINT16	PCI_Bridge_Control;			/* 0x3E */   } PCI_BRIDGE_CFG_SPACE;typedef struct   {    UINT16	PCI_Vendor_Id;					/* 0x00 */    UINT16	PCI_Device_Id;					/* 0x02 */    UINT16	PCI_PrimaryCommand;				/* 0x04 */    UINT16	PCI_PrimaryStatus;				/* 0x06 */    UINT8	PCI_Revision_ID;				/* 0x08 */    UINT8	PCI_progIf;					/* 0x09 */    UINT8	PCI_subClass;					/* 0x0A */    UINT8	PCI_baseClass;					/* 0x0B */    UINT8	PCI_Cacheline_Size;				/* 0x0C */    UINT8	PCI_Primary_Latency_Time;			/* 0x0D */    UINT8	PCI_Header_Type;				/* 0x0E */    UINT8	PCI_reserved;					/* 0x0F */    UINT32	PCI_reserved1[2];				/* 0x10 */    UINT8	PCI_Primary_Bus_Number;				/* 0x18 */    UINT8	PCI_Secondary_Bus_Number;			/* 0x19 */    UINT8	PCI_Subordinate_Bus_Number;			/* 0x1A */    UINT8	PCI_Secondary_Latency_Timer;			/* 0x1B */    UINT8	PCI_Io_Base;					/* 0x1C */    UINT8	PCI_Io_Limit;					/* 0x1D */    UINT16	PCI_Secondary_Status;				/* 0x1E */    UINT16	PCI_Memory_Base;				/* 0x20 */    UINT16	PCI_Memory_Limit;				/* 0x22 */    UINT16	PCI_Prefetchable_Memory_Base;			/* 0x24 */    UINT16	PCI_Prefetchable_Memory_Limit;			/* 0x26 */    UINT32	PCI_reserved2[3];				/* 0x28 */    UINT8	PCI_Capabilities_Pointer;			/* 0x34 */    UINT8	PCI_reserved3[3];				/* 0x35 */    UINT32	PCI_reserved4;					/* 0x38 */    UINT16	PCI_reserved5;					/* 0x3c */    UINT16	PCI_Bridge_Control;				/* 0x3E */    UINT16	PCI_Extended_Bridge_Control;			/* 0x40 */    UINT16	PCI_Secondary_IDSEL_Select;			/* 0x42 */    UINT32	PCI_Primary_Bridge_Interrupt_Status;		/* 0x44 */    UINT32	PCI_Secondary_Bridge_Interrupt_Status;		/* 0x48 */    UINT32	PCI_Secondary_Arbitration_Control;		/* 0x4C */    UINT32	PCI_Interrupt_Routing_Select;			/* 0x50 */    UINT8	PCI_Secondary_Io_Base;				/* 0x54 */    UINT8	PCI_Secondary_Io_Limit;				/* 0x55 */    UINT8	PCI_Secondary_Clock_Disable;			/* 0x56 */    UINT8	PCI_reserved6;					/* 0x57 */    UINT16	PCI_Secondary_Memory_Base;			/* 0x58 */    UINT16	PCI_Secondary_Memory_Limit;			/* 0x5A */    UINT16	PCI_Secondary_Decode_Enable;			/* 0x5C */    UINT16	PCI_Queue_Control;				/* 0x5E */    UINT32	PCI_reserved7[2];				/* 0x60 */    UINT8	PCI_Capability_Identifier;			/* 0x68 */    UINT8	PCI_Next_Item_Pointer;				/* 0x69 */    UINT16	PCI_Power_Management_Capabilities;		/* 0x6A */    UINT16	PCI_Power_Management_ControlStatus;		/* 0x6C */    UINT8	PCI_PMCSR_PCI_to_PCI_Bridge_Support;		/* 0x6E */    UINT8	PCI_reserved8;   } I80312_CFG_SPACE;typedef struct    {     UINT16	ATU_Vendor_ID;					/* 0x00 */    UINT16	ATU_Device_ID;					/* 0x02 */    UINT16	ATU_PrimaryCommand;				/* 0x04 */    UINT16	ATU_PrimaryStatus;				/* 0x06 */    UINT8	ATU_Revision_ID;				/* 0x08 */    UINT8	ATU_progIf;					/* 0x09 */    UINT8	ATU_subClass;					/* 0x0a */    UINT8	ATU_baseClass;					/* 0x0b */    UINT8	ATU_Cacheline_Size;				/* 0x0C */    UINT8	ATU_Latency_Timer;				/* 0x0D */    UINT8	ATU_Header_Type;				/* 0x0E */    UINT8	ATU_reserved1;					/* 0x0F */    UINT32	ATU_Primary_InboundBase_Address;		/* 0x10 */    UINT32	ATU_reserved2[6];				/* 0x14 */    UINT16	ATU_Subsystem_Vendor_ID;			/* 0x2C */    UINT16	ATU_Subsystem_ID;				/* 0x2E */    UINT32	ATU_Expansion_ROM_Base_Address;			/* 0x30 */    UINT8	ATU_Capabilities_Pointer;			/* 0x34 */    UINT8	ATU_reserved3[7];				/* 0x35 */    UINT8	ATU_Interrupt_Line;				/* 0x3C */    UINT8	ATU_Interrupt_Pin;				/* 0x3D */    UINT8	ATU_Minimum_Grant;				/* 0x3E */    UINT8	ATU_Maximum_Latency;				/* 0x3F */    UINT32	ATU_Primary_InboundLimit;			/* 0x40 */    UINT32	ATU_Primary_InboundTranslate_Value;		/* 0x44 */    UINT32	ATU_Secondary_InboundBase_Address;		/* 0x48 */    UINT32	ATU_Secondary_InboundLimit;			/* 0x4C */    UINT32	ATU_Secondary_Inbound_TranslateValue;		/* 0x50 */    UINT32	ATU_Primary_Outbound_Memory_Window_Value;	/* 0x54 */    UINT32	ATU_reserved4;					/* 0x58 */    UINT32	ATU_Primary_Outbound_IO_Window_Value;		/* 0x5C */    UINT32	ATU_Primary_Outbound_DAC_Window_Value;		/* 0x60 */    UINT32	ATU_Primary_Outbound_Upper_64_bit_DAC;		/* 0x64 */    UINT32	ATU_Secondary_Outbound_Memory_Window_Value;	/* 0x68 */    UINT32	ATU_Secondary_Outbound_IO_Window_Value;		/* 0x6C */    UINT32	ATU_reserved5;					/* 0x70 */    UINT32	ATU_Expansion_ROM_Limit;			/* 0x74 */    UINT32	ATU_Expansion_ROM_Translate_Value;		/* 0x78 */    UINT32	ATU_reserved6;					/* 0x7C */    UINT8	ATU_Capability_Identifier;			/* 0x80 */    UINT8	ATU_Next_Item_Pointer;				/* 0x81 */    UINT16	ATU_Power_Management_Capabilities;		/* 0x82 */    UINT16	ATU_Power_Management_ControlStatus;		/* 0x84 */    UINT32	ATU_Configuration;				/* 0x88 */    UINT32	ATU_reserved7;					/* 0x8C */    UINT32	ATU_PrimaryInterrupt_Status;			/* 0x90 */    UINT32	ATU_SecondaryInterrupt_Status;			/* 0x94 */    UINT16	ATU_SecondaryCommand;				/* 0x98 */    UINT16	ATU_SecondaryStatus;				/* 0x9A */    UINT32	ATU_Secondary_Outbound_DAC_Window_Value;	/* 0x9C */    UINT32	ATU_Secondary_Outbound_Upper_64_bit_DAC;	/* 0xA0 */    UINT32	ATU_Primary_Outbound_Configuration_Cycle_Address;/* 0xA4 */    UINT32	ATU_Secondary_Outbound_Configuration_Cycle_Address;/* 0xA8 */    UINT32	ATU_Primary_Outbound_Configuration_Cycle_Data;	/* 0xAC */    UINT32	ATU_Secondary_Outbound_Configuration_Cycle_Data;/* 0xB0 */    UINT32	ATU_PrimaryQueue_Control;			/* 0xB4 */    UINT32	ATU_SecondaryQueue_Control;			/* 0xB8 */    UINT32	ATU_PrimaryInterrupt_Mask;			/* 0xBC */    UINT32	ATU_SecondaryInterrupt_Mask;			/* 0xC0 */    } ATU_FULL_CFG_SPACE;/* * Note: * Do not use the above structure with the debugger. Reading from * the Configuration Cycle Data Registers can cause the i80200 to * take a data abort exception. */typedef struct    {     UINT16	ATU_Vendor_ID;					/* 0x00 */    UINT16	ATU_Device_ID;					/* 0x02 */    UINT16	ATU_PrimaryCommand;				/* 0x04 */    UINT16	ATU_PrimaryStatus;				/* 0x06 */    UINT8	ATU_Revision_ID;				/* 0x08 */    UINT8	ATU_progIf;					/* 0x09 */    UINT8	ATU_subClass;					/* 0x0a */    UINT8	ATU_baseClass;					/* 0x0b */    UINT8	ATU_Cacheline_Size;				/* 0x0C */    UINT8	ATU_Latency_Timer;				/* 0x0D */    UINT8	ATU_Header_Type;				/* 0x0E */    UINT8	ATU_reserved1;					/* 0x0F */    UINT32	ATU_Primary_InboundBase_Address;		/* 0x10 */    UINT32	ATU_reserved2[6];				/* 0x14 */    UINT16	ATU_Subsystem_Vendor_ID;			/* 0x2C */    UINT16	ATU_Subsystem_ID;				/* 0x2E */    UINT32	ATU_Expansion_ROM_Base_Address;			/* 0x30 */    UINT8	ATU_Capabilities_Pointer;			/* 0x34 */    UINT8	ATU_reserved3[7];				/* 0x35 */    UINT8	ATU_Interrupt_Line;				/* 0x3C */    UINT8	ATU_Interrupt_Pin;				/* 0x3D */    UINT8	ATU_Minimum_Grant;				/* 0x3E */    UINT8	ATU_Maximum_Latency;				/* 0x3F */    UINT32	ATU_Primary_InboundLimit;			/* 0x40 */    UINT32	ATU_Primary_InboundTranslate_Value;		/* 0x44 */    UINT32	ATU_Secondary_InboundBase_Address;		/* 0x48 */    UINT32	ATU_Secondary_InboundLimit;			/* 0x4C */    UINT32	ATU_Secondary_Inbound_TranslateValue;		/* 0x50 */    UINT32	ATU_Primary_Outbound_Memory_Window_Value;	/* 0x54 */    UINT32	ATU_reserved4;					/* 0x58 */    UINT32	ATU_Primary_Outbound_IO_Window_Value;		/* 0x5C */    UINT32	ATU_Primary_Outbound_DAC_Window_Value;		/* 0x60 */    UINT32	ATU_Primary_Outbound_Upper_64_bit_DAC;		/* 0x64 */    UINT32	ATU_Secondary_Outbound_Memory_Window_Value;	/* 0x68 */    UINT32	ATU_Secondary_Outbound_IO_Window_Value;		/* 0x6C */    UINT32	ATU_reserved5;					/* 0x70 */    UINT32	ATU_Expansion_ROM_Limit;			/* 0x74 */    UINT32	ATU_Expansion_ROM_Translate_Value;		/* 0x78 */    UINT32	ATU_reserved6;					/* 0x7C */    UINT8	ATU_Capability_Identifier;			/* 0x80 */    UINT8	ATU_Next_Item_Pointer;				/* 0x81 */    UINT16	ATU_Power_Management_Capabilities;		/* 0x82 */    UINT16	ATU_Power_Management_ControlStatus;		/* 0x84 */