/* config.h - Cyclone IQ80310 Eval board configuration header *//* Copyright 1996-2001 Wind River Systems, Inc. *//*modification history--------------------01n,10jul02,scm  add C++ protection...01m,21jun02,scm remove reference to brh and add AUX CLK defines...01l,02may02,scm enable mem auto size...01k,03dec01,j_b temp co to #undef INCLUDE_SW_FP for diab01j,24aug01,scm remove shell as default option...01i,22may01,scm remove windview...01h,14may01,jb  Reverting to 9600 for default baud rate01g,08may01,scm remove DEC21X40 references...01f,23feb01,scm testing...01e,23feb01,scm add support fot d-cache fast dram01d,01feb01,scm select only one MMU option, FULL or BASIC01c,29jan01,jb  Moving Nv boot offset01b,26jan01,jb  Adding Flash as NvRam support01a,26jan01,scm remove "undef" of C++ support...01h,25jan01,scm remove c++ compiler work arounds...01g,09jan01,scm new compiler check...01f,03jan01,scm test cache init...01e,18dec00,scm add HW_Init0...01d,11dec00,scm replace ARMSA2 with XScale...01c,06dec00,jb  Adding PCI and Network Support01b,29nov00,scm add MMU support...01a,05sep00,scm written*//*This module contains the configuration parameters for IQ80310*/#ifndef INCconfigh #define INCconfigh#ifdef __cplusplusextern "C" {#endif/** BSP version/revision identification, before configAll.h **/ #define BSP_VER_1_1     1	/* BSP Version */ #define BSP_VER_1_2     1 #define BSP_VERSION     "1.2"	/* Version string */ #define BSP_REV         "/2"    /* 0 for first revision */ #include "configAll.h"	/* Include the default configurations *//** Selection Macros, which might have affect later **/ #define INCLUDE_SYS_HW_INIT_0 #ifdef INCLUDE_SYS_HW_INIT_0  #ifndef _ASMLANGUAGE   IMPORT void sysHwInit0 (void);  #endif  #define SYS_HW_INIT_0() sysHwInit0 () #endif #undef INCLUDE_AUX_CLK #ifndef INCLUDE_AUX_CLK #define AUX_CLK_AVAIL        FALSE #endif #define INCLUDE_TIMESTAMP #ifdef INCLUDE_TIMESTAMP #define INCLUDE_USER_TIMESTAMP #ifdef INCLUDE_USER_TIMESTAMP  #define USER_TIMESTAMP      sysTimestamp  #define USER_TIMESTAMPLOCK  sysTimestampLock  #define USER_TIMEENABLE     sysTimestampEnable  #define USER_TIMEDISABLE    sysTimestampDisable  #define USER_TIMECONNECT    sysTimestampConnect  #define USER_TIMEPERIOD     sysTimestampPeriod  #define USER_TIMEFREQ       sysTimestampFreq #endif  /* INCLUDE_USER_TIMESTAMP */ #endif/* * if you def/undef the SECOND_LEVEL_PAGE_TABLE, you need to change the * ROM_TEXT_ADRS in the Makefile. see #define ROM_TEXT_ADRS */ #define SECOND_LEVEL_PAGE_TABLE         /* selected the two level table */ #define INCLUDE_EXC_HANDLING #define INCLUDE_EXC_TASK #define INCLUDE_RAM_PAGE_TABLE #define INCLUDE_SHOW_ROUTINES/* * defined to work with standalone image and visionClick/Probe * if defined, then define STANDALONE_NET, and undefine INCLUDE_FLASH... * also flush out DEFAULT_BOOT_LINE for IPs and target name... * * under visionClick/Probe you must convert your vxWorks.st into a "bdx" image... * * convert.exe "Z:\wpwr\target\config\iq80310\vxWorks.st" -c -m gnu -b -z * * under visionClick/Probe select from menu bar: " TOOLS/CONVERT OBJECT MODULES", * and : *   (1) add path to vxWorks.st image, *   (2) check "create symbol file for visionClick" *   (3) check "create bdx file for RAM download" * * also, in this mode iq80310 rotary switch should be set to something other than #7 */ #undef INCLUDE_HSI_PROBE/* * STANDALONE_NET must be defined for network debug with * standalone vxWorks */ #undef STANDALONE_NET/* PCI configuration */ #define INCLUDE_PCI #ifdef  INCLUDE_PCI  #define INCLUDE_END  #define INCLUDE_FEI82557END     /* include FEI END Ethernet driver */  #ifdef INCLUDE_FEI82557END   #define I82559ERMAC  { 0x00, 0xD0, 0xDE, 0xAD, 0xBE, 0xEF }  #endif/* Max number of END devices  - set to same as number of PCI slots */  #define IQ80310_MAX_END_DEVS    3  #undef WDB_COMM_TYPE  #define WDB_COMM_TYPE           WDB_COMM_END  #define INCLUDE_PING  #define INCLUDE_NET_SHOW #endif  /* INCLUDE_PCI */ #define DEFAULT_BOOT_LINE \          "fei(0,0)host:/tor/target/config/iq80310/vxWorks " \          "h=90.0.0.3 e=90.0.0.50 u=target tn=targetname"/*!!! In most situations it is not necessary to change the following macros !!!*//*** LED ***//* LED configuration */ #define SECOND_HEX_LED            /* define if 2nd HEX LED exists *//*** UART ***//* Serial port configuration */ #define INCLUDE_SERIAL #ifdef INCLUDE_SERIAL/* * If there are two UARTs. The default UART defs like NUM_TTY, CONSOLE_TTY * and CONSOLE_BAUD_RATE in configAll.h should work fine. If you change any * defaults, it might affect the WDB defs also, so cross check with WDB defs. **/ #define N_UARTS           2        /* using UART 2 for debug */ #define SECOND_UART                /* define if 2nd UART exists */ #undef  NUM_TTY #define NUM_TTY           N_UARTS #define DEFAULT_BAUD      9600 #define UART_DEFAULT_BAUD 9600 #undef  CONSOLE_TTY #define CONSOLE_TTY       0 #undef  CONSOLE_BAUD_RATE #define CONSOLE_BAUD_RATE DEFAULT_BAUD/*** WDB ***//* * Define SERIAL_DEBUG to enable debugging * via the serial ports */ #undef SERIAL_DEBUG #ifdef SERIAL_DEBUG  #define WDB_NO_BAUD_AUTO_CONFIG  #undef WDB_COMM_TYPE  #undef WDB_TTY_BAUD  #undef WDB_TTY_CHANNEL  #undef WDB_TTY_DEV_NAME  #define WDB_COMM_TYPE       WDB_COMM_SERIAL /* WDB in Serial mode */#ifdef SECOND_UART  #define WDB_TTY_BAUD        115200          /* Baud rate for WDB Connection */  #define WDB_TTY_CHANNEL     1               /* COM PORT #2 */  #define WDB_TTY_DEV_NAME    "/tyCo/1"       /* default TYCODRV_5_2 device name */#else  #define WDB_TTY_BAUD        DEFAULT_BAUD    /* Baud rate for WDB Connection */  #define WDB_TTY_CHANNEL     0               /* COM PORT #1 */  #define WDB_TTY_DEV_NAME    "/tyCo/0"       /* default TYCODRV_5_2 device name */#endif #endif /* SERIAL_DEBUG */ #endif /* INCLUDE_SERIAL *//* cache support */ #define INCLUDE_CACHE_SUPPORT #define USER_I_CACHE_ENABLE #define USER_D_CACHE_ENABLE/* StrongARM I-cache mode is a bit of an inappropriate concept, but use this */ #undef  USER_I_CACHE_MODE #define USER_I_CACHE_MODE       CACHE_WRITETHROUGH/* StrongARM has to be this, as it does not support writethrough */ #undef  USER_D_CACHE_MODE #define USER_D_CACHE_MODE       CACHE_COPYBACK/*** MMU ***//* * Initial MMU translation tabel location. Make sure it is 16K aligned. And, * since there are some memory mapped registers (MMR) between 0x1000 and * 0x2000, there shouldn't be any code or data between 0x1000 and 0x2000. * ROM_TEXT_ADRS should also be recalculted, if this MMU_TRANSLATION_BASE is * changed. */ #if 1  #undef  INCLUDE_MMU_FULL  #define INCLUDE_MMU_BASIC #else  #undef INCLUDE_MMU_BASIC  #define INCLUDE_MMU_FULL #endif #if defined(SECOND_LEVEL_PAGE_TABLE)  #define MMU_TABLE_SIZE     0x8800 #else  #define MMU_TABLE_SIZE     0x8000 #endif #define MMU_TABLE_BASE_RAM   0x00008000 /* translation tabel location */ #define MMU_TABLE_BASE_ROM   0x00004000 /* translation tabel location */ #define MMU_TABLE_END        MMU_TABLE_BASE_ROM+MMU_TABLE_SIZE #if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)  #define INCLUDE_MMU #endif #define MMU_TRANSLATION_BASE 0x00004000 /* translation tabel location */ #undef VM_PAGE_SIZE #define VM_PAGE_SIZE           4096/* Memory configuration */ #define LOCAL_MEM_AUTOSIZE                   /* run-time memory sizing */ #define LOCAL_MEM_LOCAL_ADRS	 0xa0000000   /* 0xa0000000 */ #define LOCAL_MEM_SIZE          0x02000000   /* 32Meg */ #define LOCAL_MEM_RESERVED      0x00000000   /* 0x0 *//*** RAM Information ***//* RAM starting address, RAM Size */ #define RAM_LOW_ADRS		0xa0010000/* Link Address: To where the image will be decompressed */ #define RAM_HIGH_ADRS		0xa0100000 #define SDRAM_VIRT_OFFSET       (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_RESERVED)/*** ROM Information ***//* * Boot ROM is an image written into Flash ROM and started * by the iq80310 Primary Boot Loader. * * The following parameters are defined here and in the Makefile. * They must be kept synchronized; effectively config.h depends on * Makefile. Any changes made here must be made in the Makefile and vice * versa. * * ROM_BASE_ADRS is the base of the Flash ROM * ROM_TEXT_ADRS is the entry point of the VxWorks image * ROM_SIZE is the size of the part of the Flash ROM allocated to the VxWorks *          image (block size - size of headers) * * Two other constants are used: * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM *               (uncompressed bootrom) * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc) * * The address of the Flash block being used is: *    ROM_BASE_ADRS + (block << 18)   (blocks are ROM_SIZE) * The boot ROM image is at an offset of 0xC0 into this block - 0x40 * bytes for a Flash header, 0x80 bytes for an AIF header * * The values are given as literals here to make it easier to ensure * that they are the same as those in the Makefile. */ #define ROM_BASE_ADRS	0x00000000 /* Blank 1 for booting *//* * Where the text starts in ROM, (address of _romInit), normally it will be, * MMU_TRANSLATION_BASE + 16K + additional 1K in we are using second level * translation tables. * * ROM_TEXT_ADRS = MMU_TRANSLATION_BASE + 0x4000  (+ 0x400 if second level page *                                                  table used) */ #if defined(SECOND_LEVEL_PAGE_TABLE)  #define ROM_TEXT_ADRS	MMU_TRANSLATION_BASE + 0x00004400 /* Where the text starts in ROM */ #else  #define ROM_TEXT_ADRS	MMU_TRANSLATION_BASE + 0x00004000 /* Where the text starts in ROM */ #endif /* Two level page table *//* * The size must be big enough so that *    (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) >= size of boot image * We allow up to an arbitrary 128K for the image. */ #define ROM_SIZE                0x00800000      /* size of flash ROM */ #if (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) < 0x20000  #error  ROM_ values need checking in config.h/Makefile #endif/* * ISR_STACK_SIZE is defined here rather than in ../all/configAll.h (as is * more usual) because the stack size depends on the interrupt structure of the * BSP. */ #define ISR_STACK_SIZE		0x1000   /* ISR Stack Size 4K */ #undef STACK_SAVE #define STACK_SAVE      512             /* maximum stack used to preserve *//* * make use of data cache for fast DRAM */ #undef INCLUDE_FAST_DRAM #ifdef INCLUDE_FAST_DRAM  #define FD_CACHELINE    8              /* 8 UINT32's in a cache line (32-bytes) */  #define FD_LINESPERSET 28              /* 28 available cache lines per set */  #define FD_SETS        32              /* 32 sets in data cache */  #define FD_MAX_LINES (FD_LINESPERSET * FD_SETS)      /* Max number of lines one can allocate (28 x 32) */  #define FD_ORIGIN    0xf9000000        /* location of virtual address */  #define FD_MAX_SIZE  0x7000            /* Max size for MMU table description, 28Kbytes *//* modify based on the number of cache lines you want to use as data ram... */  #define FD_NUMLINES  FD_MAX_LINES      /* set for max 28Kbytes */ #endif #include "i80312.h" /* Yavapai Chip Set */ #include "iq80310.h"	/* Board settings   *//* * Enable Flash as NvRam. Use the last 512 bytes of flash bank 1 */ #define INCLUDE_FLASH #ifdef INCLUDE_FLASH  #define FLASH_WIDTH		1  #define SYS_FLASH_TYPE		FLASH_28F008    /* Specify 8 bit 28F part */  #define FLASH_SEGMENT_SIZE	0x20000		/* sector size of 28F640 */  #define FLASH_ADRS		((IQ80310_FLASH_BANK1_BASE + IQ80310_FLASH_BANK1_SIZE) \                                  - FLASH_SEGMENT_SIZE)  #define FLASH_SIZE		FLASH_SEGMENT_SIZE  #define NV_RAM_SIZE		FLASH_SEGMENT_SIZE  #undef NV_BOOT_OFFSET  #define NV_BOOT_OFFSET		FLASH_SEGMENT_SIZE - 0x200  #undef FLASH_NO_OVERLAY #else  #define NV_RAM_SIZE		NONE #endif /* INCLUDE_FLASH */#ifdef __cplusplus}#endif#endif  /* INCconfigh */#if defined(PRJ_BUILD) #include "prjParams.h"#endif