/* sysALib.s - iq80310 system-dependent routines *//* Copyright 1996-1997 Wind River Systems, Inc. *//*modification history--------------------01l,18oct01,jb  Enabling removal of pre-pended underscores for new compilers                 (Diab/Gnu elf)01k,26jul01,scm  add routine to dump translation table base register...01j,16may01,jb  Removing FIQ support01i,15may01,jb  Adding limited FIQ support01h,14apr01,scm  add sysICUReadINTSRC - Read the INTSRC register01g,22mar01,scm  change hex display of auto memsize to reflect 2 bank simms...01f,21mar01,scm  SDRAM aut size mods...01e,20mar01,scm  correct SBR1 mask...01d,20mar01,scm  add hex display to show autosized mem...01c,28feb01,scm  remove "sysChangeTransTableBase" reference -not used...01b,22nov00,scm  correct sysInit for bootrom startup01a,11jul00,sut  written.*//*DESCRIPTIONThis module contains system-dependent routines written in assemblylanguage.This module must be the first specified in the \f3ld\f1 command used tobuild the system.  The sysInit() routine is the system start-up code.INTERNALMany routines in this module doesn't use the "c" frame pointer %r11@ !This is only for the benefit of the stacktrace facility to allow it to properly trace tasks executing within these routines.SEE ALSO: .I "ARM Architecture Reference Manual"*/#define _ASMLANGUAGE		#include "vxWorks.h"#include "regs.h"#include "arch/arm/arm.h"#include "arch/arm/mmuArmLib.h"#include "arch/arm/excArmLib.h"#include "sysLib.h"#include "config.h"        .data        .globl   VAR(copyright_wind_river)        .long    VAR(copyright_wind_river)	/* internals */	.globl	FUNC(sysInit)		/* start of system code */	.globl  FUNC(sysIntStackSplit)	.globl  FUNC(sysEnableIRQMasks)        .globl  FUNC(sysICUReadINTSRC)        .globl  FUNC(sysPhysMemSize)        .globl  FUNC(sysGetTransTblBase) 		/* externals */	.extern	FUNC(usrInit)		/* system initialization routine */	.extern	FUNC(vxSvcIntStackBase)	/* base of SVC-mode interrupt stack */	.extern	FUNC(vxSvcIntStackEnd)	/* end of SVC-mode interrupt stack */	.extern	FUNC(vxIrqIntStackBase)	/* base of IRQ-mode interrupt stack */	.extern	FUNC(vxIrqIntStackEnd)	/* end of IRQ-mode interrupt stack */	#if defined(INCLUDE_HSI_PROBE)        .globl  FUNC(probeInit)         /* start of system code */        .extern FUNC(bcopy)        .extern FUNC(bfill)/* In I80310 (Coyanosa), for various reasons the MMU has to be enabled always.- Caching Uint requires MMU- The portion of the cache is used as internal data RAM, and since cache unit  requires MMU, the MMU should be ON in order to access the internal data RAM.*/#ifdef _DIAB_TOOLMakeTransTable: .macro addr,addrSize,options,total    .if total       .if total <= 0x40           .long ((addr << addrSize) | options)           MakeTransTable (addr+1), addrSize, options, (total-1)       .else           .if total <= 0x256               MakeTransTable addr, addrSize, options, 0x40               MakeTransTable (addr+0x40), addrSize, options, (total-0x40)           .else               MakeTransTable addr, addrSize, options, 0x256               MakeTransTable (addr+0x256), addrSize, options, (total-0x256)           .endif       .endif    .endif    .endm#else /* GNU */.MACRO MakeTransTable addr=0,addrSize=0,options=0,total=0.if \total   .if \total <= 0x40       .long ((\addr << \addrSize) | \options)       MakeTransTable "(\addr+1)", \addrSize, \options, "(\total-1)"   .else       .if \total <= 0x256           MakeTransTable \addr, \addrSize, \options, 0x40           MakeTransTable "(\addr+0x40)", \addrSize, \options, "(\total-0x40)"       .else           MakeTransTable \addr, \addrSize, \options, 0x256           MakeTransTable "(\addr+0x256)", \addrSize, \options, "(\total-0x256)"       .endif   .endif.endif.ENDM#endif/* Create First Level Section Descriptor */#define SectionDesc(addr, options, total) \        MakeTransTable addr, 20, options, total/* Coarse page descriptor contains 14 bits, since it is easy to manipulate * the hex values, here the addr is shifted only by 12 bits, instead of 14bits. * So make sure that bit 11 and 10 are set to correctly in  options. * Bit 11 and 10 in options should contain the 2 LSBs from the coarse page address */#define CoarsePageDesc(addr, options) \        MakeTransTable addr, 12, options, 1#define SmallPage(addr, options, total) \        MakeTransTable addr, 12, options, total        .data        .align 4_probeInitMmuTable:#if defined(SECOND_LEVEL_PAGE_TABLE)/* 1 + 2559 + 1512 + 24 = 4096 Entries *//* First Level Coarse Page: address, options */CoarsePageDesc(8, 0x00000001)            /* 1 : Coarse Entry *//* First Level Section Descriptions: address, options, total */SectionDesc(0x001, 0x00000c02, 0x9ff)    /* 2559 : ROM Entries */#else/* 2560 + 1512 + 24 = 4096 Entries */SectionDesc(0x000, 0x00000c02, 0xa00)    /* 2560 : ROM Entries */#endifSectionDesc(0xa00, 0x00001e0e, 0x200)    /* RAM Entries */SectionDesc(0xc00, 0x00001e02, 0x3e8)    /* RAM Entries */SectionDesc(0xfe8, 0x00000c02, 0x18)     /* 24 : ROM Entries *//* 0x8000 = 0x4000 + 4000 *//* second level descriptors for fine page (4K) */#if defined(SECOND_LEVEL_PAGE_TABLE)/* Extended small page table definitions: address, options, total */SmallPage(0xa0000, 0x0000007f, 0x1)  /* 1 : 4K Page for internal data RAM */SmallPage(1, 0x00000073, 0x1)        /* 255 : 4K Page  for MMRs, and ROM */SmallPage(2, 0x0000007f, 0xfe)       /* Remaning ROM */#endif        .text        .align 4/********************************************************************************* sysInit/probeInit - (standalone alone  debug version with visionProbe)*                   - start after boot** This routine is the system start-up entry point for VxWorks in RAM, the* first code executed after booting.  It disables interrupts, sets up* the stack, and jumps to the C routine usrInit() in usrConfig.c.** The initial stack is set to grow down from the address of sysInit().  This* stack is used only by usrInit() and is never used again.  Memory for the* stack must be accounted for when determining the system load address.** NOTE: This routine should not be called by the user.** RETURNS: N/A* sysInit ()              /@ THIS IS NOT A CALLABLE ROUTINE @/*/_ARM_FUNCTION(probeInit)_ARM_FUNCTION(sysInit)/* Disable Interrupts */        MRS     r1, cpsr                /* get current status */        ORR     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */        MSR     cpsr, r1        mov     r0, #0                 /* Disable IRQ and FIQ Masks */        mcr     p13, 0, r0, c0, c0, 0        CPWAIT(r0)                     /* Wait *//* Interrupts Disabled */        adr     sp, FUNC(probeInit)  /* initialise stack pointer */        mov     fp, #0               /* initialise frame pointer *//******************************************************************************//******************************************************************************//*** Disable Write Buffer Coalescing ***/        mcr             p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */        CPWAIT(r0)                                              /* wait for the write to happen */        CPWAIT(r0)                                              /* wait for the write to happen */        mrc             p15, 0, r0, c1, c0, 1   /* Read Auxiliary Control Reg */        orr             r0, r0, #0x00000001     /* Disable Coalescing */        mcr             p15, 0, r0, c1, c0, 1   /* Write Auxiliary Control Reg */        CPWAIT(r0)                                              /* wait for the write to happen */        ldr             r2, =0x1042        ldr             r3, =0x3FF        strh            r3, [r2]        ldr             r2, =0x1040             /* quit PCI retries */        mov             r3, #0x08        strh            r3, [r2]/* Clear Low Memory */        ldr     r0, =LOCAL_MEM_LOCAL_ADRS        ldr     r1, =FUNC(probeInit)        sub     r1, r1, r0        sub     r1, r1, #64        mov     r2, #0        bl      FUNC(bfill)/* Copy Initial MMU Tables to Low Memory */        ldr     r0, =_probeInitMmuTable        ldr     r1, =(LOCAL_MEM_LOCAL_ADRS + MMU_TRANSLATION_BASE)        ldr     r2, =0x4400        bl      FUNC(bcopy)/* Enable Coprocessors CP0 and  CP13 access */        ldr             r0, =0x2001        mcr             p15, 0, r0, c15, c1, 0        mcr             p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */        CPWAIT(r0)                              /* wait for the write to happen *//* Invalidate I-Cache, D-Cache, and BTB */        mcr             p15, 0, r0, c7, c7, 0        CPWAIT(r0)                              /* Wait *//* Enable Instruction Cache */        mrc             p15, 0, r0, c1, c0, 0   /* Read Control Register*/        orr             r0, r0, #0x1000         /* Set I-Cache bit */        mcr             p15, 0, r0, c1, c0, 0   /* Write Back Control Register */        CPWAIT(r0)                              /* Wait *//* Set Translation Table Base */        ldr     r0, =(LOCAL_MEM_LOCAL_ADRS + MMU_TRANSLATION_BASE)        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */        CPWAIT(r0)                      /* Wait *//* Invalidate Instruction, Data TLBs */        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/        CPWAIT(r0)                      /* Wait *//* Set Domain Access Control Register */        ldr             r0, =0xffffffff         /* Set All 16 domains to manager access */        mcr             p15, 0, r0, c3, c0, 0   /* Set Domain Permissions *//* Enable MMU */        mrc             p15, 0, r0, c1, c0, 0   /* Read Control Register */        orr             r0, r0, #0x00000001     /* Enable MMU */        mcr             p15, 0, r0, c1, c0, 0   /* Write Back the Control Register */        CPWAIT(r0)                                                      /* Wait *//* Drain Write/Fill Buffers */        mcr     p15, 0, r0, c7, c10, 4  /* Drain */        CPWAIT(r0)                      /* Wait *//* Enable Data Cache */        mrc             p15, 0, r0, c1, c0, 0   /* Read Control Reg */        orr             r0, r0, #0x00000004             /* Enable Data Cache */        mcr             p15, 0, r0, c1, c0, 0   /* Write Back */        CPWAIT(r0)                                                      /* Wait *//* Enable Branch Target Buffer */        mrc             p15, 0, r0, c1, c0, 0   /* Read Control Reg */        orr             r0, r0, #0x00000800             /* Enable BTB */        mcr             p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */        CPWAIT(r0)                                                      /* Wait *//******************************************************************************//******************************************************************************/        mov     r0, #BOOT_CLEAR /* pass startType *//* now call usrInit */        b       FUNC(usrInit)#else /* ! INCLUDE_HSI_PROBE */	.text	.align 4/********************************************************************************* sysInit - start after boot