/* End of BUS3 */#ifdef SECOND_HEX_LED	mov		r0, #L7SEG_S & L7SEG_Dot#endif	mov		r1, #L7SEG_3 & L7SEG_Dot	bl		SevenSegDisplay/*** Data Cache Setup ***//* Drain Write/Fill Buffers */        mcr             p15, 0, r0, c7, c10, 4  /* Drain */        CPWAIT(r0)                              /* Wait *//* Enable Data Cache */	mrc	        p15, 0, r0, c1, c0, 0	/* Read Control Reg */	orr	        r0, r0, #0x00000004		/* Enable Data Cache */	mcr	        p15, 0, r0, c1, c0, 0	/* Write Back */	CPWAIT(r0)							/* Wait *//* Enable Branch Target Buffer */	mrc	        p15, 0, r0, c1, c0, 0	/* Read Control Reg */	orr	        r0, r0, #0x00000800		/* Enable BTB */	mcr	        p15, 0, r0, c1, c0, 0	/* Write Back the Control Reg */	CPWAIT(r0)							/* Wait */        bl      PrintString        .ascii  "\n"        .ascii  "=======================\n"        .ascii  "= Data Cache Setup... =\n"        .ascii  "=======================\n\0"        .align 2/* End of BUS4 */#ifdef SECOND_HEX_LED	mov		r0, #L7SEG_S & L7SEG_Dot#endif	mov		r1, #L7SEG_4 & L7SEG_Dot	bl		SevenSegDisplay/*** ECC Setup ***//* * Before accessing any portion of the memory, the memory should * have valid ECC value for every 64-bit data. Since any write transaction, * which is less then 64-bit wide will be translated into read-modify-write * transaction. Writing less than 64-bit wide data to the unscrubbed * memory will generate ECC errors. * *//* Scrubbing Memory */	ldr		r11, =IQ80310_SDRAM_BASE_ADRS   /* base address of SDRAM */	mov		r12, r4                         /* size of the memory to scrub */	mov		r10, r4                         /* save size of the memory */	mov		r0, #0x00000000	mov		r1, #0x00000000	mov		r2, #0x00000000	mov		r3, #0x00000000	mov		r4, #0x00000000	mov		r5, #0x00000000	mov		r6, #0x00000000	mov		r7, #0x00000000ScrubNext32Bytes:        stmia   	r11!, {r0-r7}           /* Write 64-bit wide data */        subs    	r12, r12, #0x00000020        bne     	ScrubNext32Bytes        /* Write Next 32 bytes */ScrubDone:        bl      PrintString        .ascii  "\n"        .ascii  "======================\n"        .ascii  "= Memory Scrubbed... =\n"        .ascii  "======================\n\0"        .align 2/* End of BUS5 */#ifdef SECOND_HEX_LED	mov		r0, #L7SEG_S & L7SEG_Dot#endif	mov		r1, #L7SEG_5 & L7SEG_Dot	bl		SevenSegDisplay/* Clean (Write Back) the Data Cache by Allocating non-existent memory address tags * for the cache line. Since tags are mapped into a non-existen memory address, it is * guaranteed that all cache lines will be cleaned */	ldr		r1, =LOCAL_MEM_LOCAL_ADRS               /* use a CACHEABLE area of */	add		r1, r1, r10                             /* add in DRAM_SIZE */	mov		r0, #SZ_1K                              /* the memory map above SDRAM */AllocNextDCacheLine:	mcr		p15, 0, r1, c7, c2, 5	/* Allocate a DCache Line */	add		r1, r1, #SZ_32     	/* increment the address to the next cache line */	subs		r0, r0, #1		/* decrement the loop count */	bne		AllocNextDCacheLine/* End of BUS6 */#ifdef SECOND_HEX_LED	mov		r0, #L7SEG_S & L7SEG_Dot#endif	mov		r1, #L7SEG_6 & L7SEG_Dot	bl		SevenSegDisplay/* Merged into one loop *//* DRAM_BASE + DRAM_SIZE + DCACHE_SIZE */	ldr		r2, =(LOCAL_MEM_LOCAL_ADRS+SZ_32K)       /* DRAM_BASE + DCACHE_SIZE */	add		r2, r2, r10                              /* add in DRAM_SIZE */	mov		r0, #SZ_64AllocNextMiniDCacheLine:	mcr		p15, 0, r2, c7, c2, 5		/* setup dcache */	add		r2, r2, #SZ_32                  /* increment address by 32 */	subs		r0, r0, #1			/* decrement the loop */	bne		AllocNextMiniDCacheLine		/* continue *//* Invalidate Whole Data Cache */	mcr		p15, 0, r0, c7, c6, 0	CPWAIT(r0)/* Drain Write/Fill buffer. I think this might generate 64-bit wide * data write for ECC generation */	mcr		p15, 0, r0, c7, c10, 4		/* Drain write/fill buffers */	CPWAIT(r0)        bl      PrintString        .ascii  "\n"        .ascii  "=================================\n"        .ascii  "= Caches Allocated & Cleared... =\n"        .ascii  "=================================\n\0"        .align 2/* Enable ECC on Coy, required for Yavapai */	mcr		p15, 0, r0, c7, c10, 4		/* Drain write/fill buffers */	CPWAIT(r0)	BCUWAIT(r0)							/* Wait if BCU busy *//* add in multi-bit error reporting */        mrc     p13, 0, r0, c0, c1, 0           /* disable ECC */        and     r0, r0, #(-1-8)        mcr     p13, 0, r0, c0, c1, 0        orr     r0, r0, #6                      /* enable single-bit correction, multi-bit detection */        mcr     p13, 0, r0, c0, c1, 0        orr     r0, r0, #8                      /* enable ECC */        mcr     p13, 0, r0, c0, c1, 0	BCUWAIT(r0)                                 /* Wait if BCU busy */        /* Enable ECC circuitry in Yavapai */        ldr     r1, =I80312_ECCR        ldr     r0, =ECC_CORR_ENABLE            /* Enable single bit ECC Correction (Reporting Disabled) */        str     r0, [r1, #0]        bl      PrintString        .ascii  "\n"        .ascii  "=================================\n"        .ascii  "= ECC circuitry Enable...       =\n"        .ascii  "=================================\n\0"        .align 2/* End of BUS7 */#ifdef SECOND_HEX_LED	mov		r0, #L7SEG_S & L7SEG_Dot#endif	mov		r1, #L7SEG_7 & L7SEG_Dot	bl		SevenSegDisplay        b               vxWorks_bootwarm_start:/* Disable Interrupts */        MRS     r1, cpsr                /* get current status */        ORR     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */        MSR     cpsr, r1        mov     r0, #0                  /* Disable IRQ and FIQ Masks */        mcr     p13, 0, r0, c0, c0, 0/* Interrupts Disabled */        ldr     r0, =IQ80310_PAL_INT_STATUS_MASK /* Zero-out Interrupt Mask */        mov     r1, #0x1f        strb    r1, [r0]/* flush instruction and data TLBs */        mcr     p15, 0, r0, c8, c7, 0        CPWAIT  (r0)                    /* Wait *//* Enable Instruction Cache */        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register*/        orr     r0, r0, #0x1000         /* Set I-Cache bit */        mcr     p15, 0, r0, c1, c0, 0   /* Write Back Control Register */        CPWAIT(r0)                      /* Wait *//* Set Translation Table Base */        ldr     r0, =MMU_TRANSLATION_BASE        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register *//* Invalidate Instruction, Data TLBs */        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/        CPWAIT(r0)                      /* Wait *//* Set Domain Access Control Register */        ldr     r0, =0xffffffff         /* Set All 16 domains to manager access */        mcr     p15, 0, r0, c3, c0, 0   /* Set Domain Permissions *//* Enable MMU */        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register */        orr     r0, r0, #0x00000001     /* Enable MMU */        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Register */        CPWAIT(r0)                      /* Wait *//* Drain Write/Fill Buffers */        mcr     p15, 0, r0, c7, c10, 4  /* Drain */        CPWAIT(r0)                      /* Wait *//* Enable Data Cache */        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */        orr     r0, r0, #0x00000004             /* Enable Data Cache */        mcr     p15, 0, r0, c1, c0, 0   /* Write Back */        CPWAIT(r0)                      /* Wait *//* Enable Branch Target Buffer */        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */        orr     r0, r0, #0x00000800             /* Enable BTB */        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */        CPWAIT(r0)                      /* Wait *//******************************************************************************//******************************************************************************/vxWorks_boot:        bl      PrintString        .ascii  "\n"        .ascii  "==================================\n"        .ascii  "= vxWorks_boot: Moving to RAM... =\n"        .ascii  "==================================\n\0"        .align 2        bl      PrintString        .ascii  "\nBOOT Type:     \0"        .align 2        mov     r0, r8        bl      PrintHex32        bl      PrintString        .ascii  "\nSTACK_ADDR:     \0"        .align 2        ldr     r0, L$STACK_ADDR        bl      PrintHex32        bl      PrintString        .ascii  "\nStrtInRam:     \0"        .align 2        ldr     r0, L$StrtInRam        bl      PrintHex32        bl      PrintString        .ascii  "\n\0"        .align 2/*  Now jump to the code that starts the whole vxWorks boot process */	mov	r0, r8	ldr	sp, L$STACK_ADDR	ldr	pc, L$StrtInRam/******************************************************************************//******************************************************************************//* r0 :	MSB * r1 :	LSB * r2 :	 Used */SevenSegDisplay:#ifdef SECOND_HEX_LED        ldr             r2, =HEX_DISPLAY2        strb            r1, [r2]#endif        ldr             r2, =HEX_DISPLAY1        strb            r0, [r2]	mov	        pc, lr/************************** UART Helpers ******************************************/UARTVString:        ldr             r10, =SERIAL_DISPLAYUARTNextChar:        ldrb            r1, [r0], #1        teq             r1, #0        beq             URATTxDone        and             r1, r1, #0xff10:        ldrb            r2, [r10, #UART_LineStatus]        tst             r2, #UARTLSR_TXHoldingEmpty        beq             10b        strb            r1, [r10, #UART_Transmit]        B               UARTNextCharURATTxDone:        ldr             r10, =SERIAL_DISPLAY        mov             r1, #1320:        ldrb            r2, [r10, #UART_LineStatus]        tst             r2, #UARTLSR_TXHoldingEmpty        beq             20b        strb            r1, [r10, #UART_Transmit]        mov             r1, #1030:        ldrb            r2, [r10, #UART_LineStatus]        tst             r2, #UARTLSR_TXHoldingEmpty        beq             30b        strb            r1, [r10, #UART_Transmit]        mov             pc, lr/*Bettter don't use r0, r1, r2 and r10sUses r0, r10*/UARTStart:        ldr             r10, =SERIAL_DISPLAY        ldr             r0, =DMABodgeDelayUARTDelay:        subs            r0, r0, #1        bne             UARTDelay    /* enable access to divisor registers */        mov             r0, #UARTLCR_DivisorLatchAccess        strb            r0, [r10, #UART_LineControl]        ldr             r0, =DMABodgeDelayUARTDelay1:        subs            r0, r0, #1        bne             UARTDelay1    /* select baud rate */        ldr             r0, =BaudRateDivisor_115200        strb            r0, [r10, #UART_DivisorLatchLSB]        mov             r0, r0, LSR #8        strb            r0, [r10, #UART_DivisorLatchMSB]    /* 8 data, 1 stop, no parity */        mov             r0, #UARTLCR_CharLength8 | UARTLCR_StopBits1    /* also disable access to divisor regs */        strb            r0, [r10, #UART_LineControl]    /* no irqs */        mov             r0, #0        strb            r0, [r10, #UART_InterruptEnable]        mov             r0, #UARTFCR_Enable