library verilog;use verilog.vl_types.all;entity main_seed_precomputation is    port(        a               : in     vl_logic_vector(13 downto 0);        b               : in     vl_logic_vector(11 downto 0);        c               : in     vl_logic_vector(11 downto 0);        IsIntra16x16    : in     vl_logic;        main_seed       : out    vl_logic_vector(15 downto 0)    );end main_seed_precomputation;