/* system.h * * Machine generated for a CPU named "cpu_0" as defined in: * d:\altera\myPS2VGAproject\first_cpu\software\hello_world_0_syslib\..\..\niose_cpu_0.ptf * * Generated: 2009-04-14 12:22:23.125 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "niose_cpu_0"#define ALT_CPU_NAME "cpu_0"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONEII"#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"#define ALT_STDIN_BASE 0x01802030#define ALT_STDIN_DEV jtag_uart#define ALT_STDIN_PRESENT#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"#define ALT_STDOUT_BASE 0x01802030#define ALT_STDOUT_DEV jtag_uart#define ALT_STDOUT_PRESENT#define ALT_STDERR "/dev/jtag_uart"#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"#define ALT_STDERR_BASE 0x01802030#define ALT_STDERR_DEV jtag_uart#define ALT_STDERR_PRESENT#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "fast"#define NIOS2_BIG_ENDIAN 0#define NIOS2_ICACHE_SIZE 4096#define NIOS2_DCACHE_SIZE 2048#define NIOS2_ICACHE_LINE_SIZE 32#define NIOS2_ICACHE_LINE_SIZE_LOG2 5#define NIOS2_DCACHE_LINE_SIZE 32#define NIOS2_DCACHE_LINE_SIZE_LOG2 5#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x00800020#define NIOS2_RESET_ADDR 0x01400000#define NIOS2_BREAK_ADDR 0x01801020#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_CFI_FLASH#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER#define __ALTERA_AVALON_TRI_STATE_BRIDGE#define __ALTERA_AVALON_UART#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_SYSID#define __ALTERA_AVALON_PIO#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER/* * cfi_flash configuration * */#define CFI_FLASH_NAME "/dev/cfi_flash"#define CFI_FLASH_TYPE "altera_avalon_cfi_flash"#define CFI_FLASH_BASE 0x01400000#define CFI_FLASH_SPAN 4194304#define CFI_FLASH_SETUP_VALUE 40#define CFI_FLASH_WAIT_VALUE 160#define CFI_FLASH_HOLD_VALUE 40#define CFI_FLASH_TIMING_UNITS "ns"#define CFI_FLASH_UNIT_MULTIPLIER 1#define CFI_FLASH_SIZE 4194304#define ALT_MODULE_CLASS_cfi_flash altera_avalon_cfi_flash/* * sdram configuration * */#define SDRAM_NAME "/dev/sdram"#define SDRAM_TYPE "altera_avalon_new_sdram_controller"#define SDRAM_BASE 0x00800000#define SDRAM_SPAN 8388608#define SDRAM_REGISTER_DATA_IN 1#define SDRAM_SIM_MODEL_BASE 1#define SDRAM_SDRAM_DATA_WIDTH 16#define SDRAM_SDRAM_ADDR_WIDTH 12#define SDRAM_SDRAM_ROW_WIDTH 12#define SDRAM_SDRAM_COL_WIDTH 8#define SDRAM_SDRAM_NUM_CHIPSELECTS 1#define SDRAM_SDRAM_NUM_BANKS 4#define SDRAM_REFRESH_PERIOD 15.625#define SDRAM_POWERUP_DELAY 100.0#define SDRAM_CAS_LATENCY 3#define SDRAM_T_RFC 70.0#define SDRAM_T_RP 20.0#define SDRAM_T_MRD 3#define SDRAM_T_RCD 20.0#define SDRAM_T_AC 5.5#define SDRAM_T_WR 14.0#define SDRAM_INIT_REFRESH_COMMANDS 2#define SDRAM_INIT_NOP_DELAY 0.0#define SDRAM_SHARED_DATA 0#define SDRAM_SDRAM_BANK_WIDTH 2#define SDRAM_TRISTATE_BRIDGE_SLAVE ""#define SDRAM_STARVATION_INDICATOR 0#define SDRAM_IS_INITIALIZED 1#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller/* * tristate_bridge configuration * */#define TRISTATE_BRIDGE_NAME "/dev/tristate_bridge"#define TRISTATE_BRIDGE_TYPE "altera_avalon_tri_state_bridge"#define ALT_MODULE_CLASS_tristate_bridge altera_avalon_tri_state_bridge/* * uart configuration * */#define UART_NAME "/dev/uart"#define UART_TYPE "altera_avalon_uart"#define UART_BASE 0x01802000#define UART_SPAN 32#define UART_IRQ 1#define UART_BAUD 115200#define UART_DATA_BITS 8#define UART_FIXED_BAUD 0#define UART_PARITY 'N'#define UART_STOP_BITS 1#define UART_USE_CTS_RTS 0#define UART_USE_EOP_REGISTER 0#define UART_SIM_TRUE_BAUD 0#define UART_SIM_CHAR_STREAM ""#define UART_FREQ 50000000#define ALT_MODULE_CLASS_uart altera_avalon_uart/* * jtag_uart configuration * */#define JTAG_UART_NAME "/dev/jtag_uart"#define JTAG_UART_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_BASE 0x01802030#define JTAG_UART_SPAN 8#define JTAG_UART_IRQ 2#define JTAG_UART_WRITE_DEPTH 64#define JTAG_UART_READ_DEPTH 64#define JTAG_UART_WRITE_THRESHOLD 8#define JTAG_UART_READ_THRESHOLD 8#define JTAG_UART_READ_CHAR_STREAM ""#define JTAG_UART_SHOWASCII 1#define JTAG_UART_READ_LE 0#define JTAG_UART_WRITE_LE 0#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart/* * sysid configuration * */#define SYSID_NAME "/dev/sysid"#define SYSID_TYPE "altera_avalon_sysid"#define SYSID_BASE 0x01802038#define SYSID_SPAN 8#define SYSID_ID 651160472u#define SYSID_TIMESTAMP 1239682353u#define SYSID_REGENERATE_VALUES 0#define ALT_MODULE_CLASS_sysid altera_avalon_sysid/* * pio configuration * */#define PIO_NAME "/dev/pio"#define PIO_TYPE "altera_avalon_pio"#define PIO_BASE 0x01802020#define PIO_SPAN 16#define PIO_DO_TEST_BENCH_WIRING 0#define PIO_DRIVEN_SIM_VALUE 0#define PIO_HAS_TRI 0#define PIO_HAS_OUT 1#define PIO_HAS_IN 0#define PIO_CAPTURE 0#define PIO_DATA_WIDTH 4#define PIO_EDGE_TYPE "NONE"#define PIO_IRQ_TYPE "NONE"#define PIO_BIT_CLEARING_EDGE_REGISTER 0#define PIO_FREQ 50000000#define ALT_MODULE_CLASS_pio altera_avalon_pio/* * epcs_controller configuration * */#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"#define EPCS_CONTROLLER_BASE 0x01801800#define EPCS_CONTROLLER_SPAN 2048#define EPCS_CONTROLLER_IRQ 0#define EPCS_CONTROLLER_DATABITS 8#define EPCS_CONTROLLER_TARGETCLOCK 20#define EPCS_CONTROLLER_CLOCKUNITS "MHz"#define EPCS_CONTROLLER_CLOCKMULT 1000000#define EPCS_CONTROLLER_NUMSLAVES 1#define EPCS_CONTROLLER_ISMASTER 1#define EPCS_CONTROLLER_CLOCKPOLARITY 0#define EPCS_CONTROLLER_CLOCKPHASE 0#define EPCS_CONTROLLER_LSBFIRST 0#define EPCS_CONTROLLER_EXTRADELAY 0#define EPCS_CONTROLLER_TARGETSSDELAY 100#define EPCS_CONTROLLER_DELAYUNITS "us"#define EPCS_CONTROLLER_DELAYMULT "1e-006"#define EPCS_CONTROLLER_PREFIX "epcs_"#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200#define EPCS_CONTROLLER_USE_ASMI_ATOM 1#define EPCS_CONTROLLER_CLOCKUNIT "kHz"#define EPCS_CONTROLLER_DELAYUNIT "us"#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller/* * system library configuration * */#define ALT_MAX_FD 32#define ALT_SYS_CLK none#define ALT_TIMESTAMP_CLK none/* * Devices associated with code sections. * */#define ALT_TEXT_DEVICE       SDRAM#define ALT_RODATA_DEVICE     SDRAM#define ALT_RWDATA_DEVICE     SDRAM#define ALT_EXCEPTIONS_DEVICE SDRAM#define ALT_RESET_DEVICE      CFI_FLASH#endif /* __SYSTEM_H_ */