?? cpld_qq2812.pin
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-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10k Ohm resistor
-- to GND or tie all pins together and connect through a single 10k Ohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- NON_MIGRATABLE: This pin cannot be migrated.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
CHIP "CPLD_QQ2812" ASSIGNED TO AN: EPM3256AFC256-10
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
NC : A1 : : : : :
NC : A2 : : : : :
GND : A3 : gnd : : : :
OUT[8] : A4 : output : 3.3-V LVTTL : : : N
LED[0] : A5 : output : 3.3-V LVTTL : : : N
NC : A6 : : : : :
OUT[2] : A7 : output : 3.3-V LVTTL : : : N
GND : A8 : gnd : : : :
DSP_Add[3] : A9 : input : 3.3-V LVTTL : : : N
RESERVED : A10 : : : : :
RESERVED : A11 : : : : :
NC : A12 : : : : :
NC : A13 : : : : :
NC : A14 : : : : :
NC : A15 : : : : :
NC : A16 : : : : :
NC : B1 : : : : :
NC : B2 : : : : :
VCCIO : B3 : power : : 3.3V : :
SIDIN : B4 : output : 3.3-V LVTTL : : : N
VCCIO : B5 : power : : 3.3V : :
LCD_Data[7] : B6 : output : 3.3-V LVTTL : : : N
LCD_Data[2] : B7 : output : 3.3-V LVTTL : : : N
LED[2] : B8 : output : 3.3-V LVTTL : : : N
VCCINT : B9 : power : : 3.3V : :
GND : B10 : gnd : : : :
RESERVED : B11 : : : : :
IN[11] : B12 : input : 3.3-V LVTTL : : : N
RESERVED : B13 : : : : :
RESERVED : B14 : : : : :
NC : B15 : : : : :
NC : B16 : : : : :
NC : C1 : : : : :
GND : C2 : gnd : : : :
RESERVED : C3 : : : : :
DSP_Data[0] : C4 : bidir : 3.3-V LVTTL : : : N
LCD_Data[1] : C5 : output : 3.3-V LVTTL : : : N
OUT[0] : C6 : output : 3.3-V LVTTL : : : N
CANRX : C7 : output : 3.3-V LVTTL : : : N
VCCINT : C8 : power : : 3.3V : :
GND : C9 : gnd : : : :
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