Version 9.0 Build 132 02/25/2009 SJ Full Version
28
1721
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
CPLD_QQ2812
# storage
db|CPLD_QQ2812.(0).cnf
db|CPLD_QQ2812.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
CPLD_QQ2812.v
524fbaf43e57b6c57bc32a651e23c8b
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence
BUZZERAdd6'h00LedAdd6'h01EAdd6'h02RSAdd6'h03LCDDataAdd6'h04SPI_CSAdd6'h05SIAdd6'h06W_IO_OUT_L6'h0eW_IO_OUT_H6'h0fPATENDAdd6'h07R_IO_IN_L6'h0eR_IO_IN_H6'h0fINT1Add6'h01NMIAdd6'h02R_FIFO_Sta6'h03R_PA_Sta6'h04
# end
# complete