{ "Info" "ITDB_TSU_RESULT" "DSP_Data_reg\[4\] EXINT\[4\] RD 21.500 ns register " "Info: tsu for register \"DSP_Data_reg\[4\]\" (data pin = \"EXINT\[4\]\", clock pin = \"RD\") is 21.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.800 ns + Longest pin register " "Info: + Longest pin to register delay is 21.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns EXINT\[4\] 1 PIN PIN_F9 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_F9; Fanout = 4; PIN Node = 'EXINT\[4\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { EXINT[4] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 8.500 ns Equal0~1 2 COMB LC97 16 " "Info: 2: + IC(3.300 ns) + CELL(4.000 ns) = 8.500 ns; Loc. = LC97; Fanout = 16; COMB Node = 'Equal0~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { EXINT[4] Equal0~1 } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 172 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.300 ns) 15.800 ns EXINT_reg\[4\]~43 3 COMB LOOP LC31 4 " "Info: 3: + IC(0.000 ns) + CELL(7.300 ns) = 15.800 ns; Loc. = LC31; Fanout = 4; COMB LOOP Node = 'EXINT_reg\[4\]~43'" { { "Info" "ITDB_PART_OF_SCC" "EXINT_reg\[4\]~43 LC31 " "Info: Loc. = LC31; Node \"EXINT_reg\[4\]~43\"" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { EXINT_reg[4]~43 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { EXINT_reg[4]~43 } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.300 ns" { Equal0~1 EXINT_reg[4]~43 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.800 ns) 21.800 ns DSP_Data_reg\[4\] 4 REG LC24 8 " "Info: 4: + IC(3.200 ns) + CELL(2.800 ns) = 21.800 ns; Loc. = LC24; Fanout = 8; REG Node = 'DSP_Data_reg\[4\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { EXINT_reg[4]~43 DSP_Data_reg[4] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.300 ns ( 70.18 % ) " "Info: Total cell delay = 15.300 ns ( 70.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.500 ns ( 29.82 % ) " "Info: Total interconnect delay = 6.500 ns ( 29.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "21.800 ns" { EXINT[4] Equal0~1 EXINT_reg[4]~43 DSP_Data_reg[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "21.800 ns" { EXINT[4] {} EXINT[4]~out {} Equal0~1 {} EXINT_reg[4]~43 {} DSP_Data_reg[4] {} } { 0.000ns 0.000ns 3.300ns 0.000ns 3.200ns } { 0.000ns 1.200ns 4.000ns 7.300ns 2.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD destination 3.200 ns - Shortest register " "Info: - Shortest clock path from clock \"RD\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns RD 1 CLK PIN_D8 11 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_D8; Fanout = 11; CLK Node = 'RD'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns DSP_Data_reg\[4\] 2 REG LC24 8 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC24; Fanout = 8; REG Node = 'DSP_Data_reg\[4\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { RD DSP_Data_reg[4] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "21.800 ns" { EXINT[4] Equal0~1 EXINT_reg[4]~43 DSP_Data_reg[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "21.800 ns" { EXINT[4] {} EXINT[4]~out {} Equal0~1 {} EXINT_reg[4]~43 {} DSP_Data_reg[4] {} } { 0.000ns 0.000ns 3.300ns 0.000ns 3.200ns } { 0.000ns 1.200ns 4.000ns 7.300ns 2.800ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "RD DSP_Data\[1\] DSP_Data_reg\[1\] 6.400 ns register " "Info: tco from clock \"RD\" to destination pin \"DSP_Data\[1\]\" through register \"DSP_Data_reg\[1\]\" is 6.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD source 3.200 ns + Longest register " "Info: + Longest clock path from clock \"RD\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns RD 1 CLK PIN_D8 11 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_D8; Fanout = 11; CLK Node = 'RD'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns DSP_Data_reg\[1\] 2 REG LC6 14 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC6; Fanout = 14; REG Node = 'DSP_Data_reg\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { RD DSP_Data_reg[1] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[1] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DSP_Data_reg\[1\] 1 REG LC6 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 14; REG Node = 'DSP_Data_reg\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_Data_reg[1] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns DSP_Data\[1\] 2 PIN PIN_D5 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_D5; Fanout = 0; PIN Node = 'DSP_Data\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { DSP_Data_reg[1] DSP_Data[1] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { DSP_Data_reg[1] DSP_Data[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { DSP_Data_reg[1] {} DSP_Data[1] {} } { 0.000ns 0.000ns } { 0.000ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[1] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { DSP_Data_reg[1] DSP_Data[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { DSP_Data_reg[1] {} DSP_Data[1] {} } { 0.000ns 0.000ns } { 0.000ns 1.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "DSP_Add\[2\] DSP_Data\[1\] 17.200 ns Longest " "Info: Longest tpd from source pin \"DSP_Add\[2\]\" to destination pin \"DSP_Data\[1\]\" is 17.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns DSP_Add\[2\] 1 PIN PIN_L16 92 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_L16; Fanout = 92; PIN Node = 'DSP_Add\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { DSP_Add[2] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(4.000 ns) 9.000 ns DSP_Data~22 2 COMB LC227 8 " "Info: 2: + IC(3.800 ns) + CELL(4.000 ns) = 9.000 ns; Loc. = LC227; Fanout = 8; COMB Node = 'DSP_Data~22'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.800 ns" { DSP_Add[2] DSP_Data~22 } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(5.000 ns) 17.200 ns DSP_Data\[1\] 3 PIN PIN_D5 0 " "Info: 3: + IC(3.200 ns) + CELL(5.000 ns) = 17.200 ns; Loc. = PIN_D5; Fanout = 0; PIN Node = 'DSP_Data\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "8.200 ns" { DSP_Data~22 DSP_Data[1] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.200 ns ( 59.30 % ) " "Info: Total cell delay = 10.200 ns ( 59.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 40.70 % ) " "Info: Total interconnect delay = 7.000 ns ( 40.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "17.200 ns" { DSP_Add[2] DSP_Data~22 DSP_Data[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "17.200 ns" { DSP_Add[2] {} DSP_Add[2]~out {} DSP_Data~22 {} DSP_Data[1] {} } { 0.000ns 0.000ns 3.800ns 3.200ns } { 0.000ns 1.200ns 4.000ns 5.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "DSP_Data_reg\[7\] CS1 RD -1.900 ns register " "Info: th for register \"DSP_Data_reg\[7\]\" (data pin = \"CS1\", clock pin = \"RD\") is -1.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RD destination 3.200 ns + Longest register " "Info: + Longest clock path from clock \"RD\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns RD 1 CLK PIN_D8 11 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_D8; Fanout = 11; CLK Node = 'RD'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns DSP_Data_reg\[7\] 2 REG LC17 1 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC17; Fanout = 1; REG Node = 'DSP_Data_reg\[7\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { RD DSP_Data_reg[7] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "1.200 ns + " "Info: + Micro hold delay of destination is 1.200 ns" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns CS1 1 PIN PIN_G14 53 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_G14; Fanout = 53; PIN Node = 'CS1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS1 } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.300 ns) 6.300 ns DSP_Data_reg\[7\] 2 REG LC17 1 " "Info: 2: + IC(3.800 ns) + CELL(1.300 ns) = 6.300 ns; Loc. = LC17; Fanout = 1; REG Node = 'DSP_Data_reg\[7\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { CS1 DSP_Data_reg[7] } "NODE_NAME" } } { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 39.68 % ) " "Info: Total cell delay = 2.500 ns ( 39.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 60.32 % ) " "Info: Total interconnect delay = 3.800 ns ( 60.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { CS1 DSP_Data_reg[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { CS1 {} CS1~out {} DSP_Data_reg[7] {} } { 0.000ns 0.000ns 3.800ns } { 0.000ns 1.200ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { RD DSP_Data_reg[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { RD {} RD~out {} DSP_Data_reg[7] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { CS1 DSP_Data_reg[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { CS1 {} CS1~out {} DSP_Data_reg[7] {} } { 0.000ns 0.000ns 3.800ns } { 0.000ns 1.200ns 1.300ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 16 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Peak virtual memory: 131 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 21 17:16:31 2009 " "Info: Processing ended: Sat Mar 21 17:16:31 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}