{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 21 17:16:05 2009 " "Info: Processing started: Sat Mar 21 17:16:05 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CPLD_QQ2812 -c CPLD_QQ2812 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CPLD_QQ2812 -c CPLD_QQ2812" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "CPLD_QQ2812.v(217) " "Warning (10273): Verilog HDL warning at CPLD_QQ2812.v(217): extended using \"x\" or \"z\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 217 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CPLD_QQ2812.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CPLD_QQ2812.v" { { "Info" "ISGN_ENTITY_NAME" "1 CPLD_QQ2812 " "Info: Found entity 1: CPLD_QQ2812" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 27 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "CPLD_QQ2812 " "Info: Elaborating entity \"CPLD_QQ2812\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "EXINT_reg CPLD_QQ2812.v(170) " "Warning (10240): Verilog HDL Always Construct warning at CPLD_QQ2812.v(170): inferring latch(es) for variable \"EXINT_reg\", which holds its previous value in one or more paths through the always construct" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 170 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "NMI1_reg CPLD_QQ2812.v(183) " "Warning (10240): Verilog HDL Always Construct warning at CPLD_QQ2812.v(183): inferring latch(es) for variable \"NMI1_reg\", which holds its previous value in one or more paths through the always construct" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 183 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "NMI2_reg CPLD_QQ2812.v(183) " "Warning (10240): Verilog HDL Always Construct warning at CPLD_QQ2812.v(183): inferring latch(es) for variable \"NMI2_reg\", which holds its previous value in one or more paths through the always construct" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 183 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CPLD_QQ2812.v(197) " "Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(197): truncated value with size 32 to match size of target (1)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CPLD_QQ2812.v(198) " "Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(198): truncated value with size 32 to match size of target (1)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 198 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CPLD_QQ2812.v(199) " "Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(199): truncated value with size 32 to match size of target (1)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 199 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CPLD_QQ2812.v(200) " "Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(200): truncated value with size 32 to match size of target (1)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 200 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "NMI2_reg CPLD_QQ2812.v(193) " "Info (10041): Inferred latch for \"NMI2_reg\" at CPLD_QQ2812.v(193)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 193 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "NMI1_reg CPLD_QQ2812.v(193) " "Info (10041): Inferred latch for \"NMI1_reg\" at CPLD_QQ2812.v(193)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 193 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "EXINT_reg\[0\] CPLD_QQ2812.v(179) " "Info (10041): Inferred latch for \"EXINT_reg\[0\]\" at CPLD_QQ2812.v(179)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "EXINT_reg\[1\] CPLD_QQ2812.v(179) " "Info (10041): Inferred latch for \"EXINT_reg\[1\]\" at CPLD_QQ2812.v(179)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "EXINT_reg\[2\] CPLD_QQ2812.v(179) " "Info (10041): Inferred latch for \"EXINT_reg\[2\]\" at CPLD_QQ2812.v(179)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "EXINT_reg\[3\] CPLD_QQ2812.v(179) " "Info (10041): Inferred latch for \"EXINT_reg\[3\]\" at CPLD_QQ2812.v(179)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "EXINT_reg\[4\] CPLD_QQ2812.v(179) " "Info (10041): Inferred latch for \"EXINT_reg\[4\]\" at CPLD_QQ2812.v(179)" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 179 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 -1}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "WR " "Info: Promoted clock signal driven by pin \"WR\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0 -1} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "RD " "Info: Promoted clock signal driven by pin \"RD\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0 -1}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0 -1}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "IFCLK " "Warning (15610): No output dependent on input pin \"IFCLK\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 35 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLKOUT " "Warning (15610): No output dependent on input pin \"CLKOUT\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 35 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RXB " "Warning (15610): No output dependent on input pin \"RXB\"" {  } { { "CPLD_QQ2812.v" "" { Text "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v" 39 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "180 " "Info: Implemented 180 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "51 " "Info: Implemented 51 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "49 " "Info: Implemented 49 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_MCELLS" "72 " "Info: Implemented 72 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.map.smsg " "Info: Generated suppressed messages file E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Info: Peak virtual memory: 172 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 21 17:16:09 2009 " "Info: Processing ended: Sat Mar 21 17:16:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}