|CPLD_QQ2812
DSP_Add[0] => Equal1.IN11
DSP_Add[0] => Decoder0.IN5
DSP_Add[1] => Equal1.IN10
DSP_Add[1] => Decoder0.IN4
DSP_Add[2] => Equal1.IN9
DSP_Add[2] => Decoder0.IN3
DSP_Add[3] => Equal1.IN8
DSP_Add[3] => Decoder0.IN2
DSP_Add[4] => Equal1.IN7
DSP_Add[4] => Decoder0.IN1
DSP_Add[5] => Equal1.IN6
DSP_Add[5] => Decoder0.IN0
DSP_Data[0] <= DSP_Data[0]~7
DSP_Data[1] <= DSP_Data[1]~6
DSP_Data[2] <= DSP_Data[2]~5
DSP_Data[3] <= DSP_Data[3]~4
DSP_Data[4] <= DSP_Data[4]~3
DSP_Data[5] <= DSP_Data[5]~2
DSP_Data[6] <= DSP_Data[6]~1
DSP_Data[7] <= DSP_Data[7]~0
WR => OUT_reg[15].CLK
WR => OUT_reg[14].CLK
WR => OUT_reg[13].CLK
WR => OUT_reg[12].CLK
WR => OUT_reg[11].CLK
WR => OUT_reg[10].CLK
WR => OUT_reg[9].CLK
WR => OUT_reg[8].CLK
WR => OUT_reg[7].CLK
WR => OUT_reg[6].CLK
WR => OUT_reg[5].CLK
WR => OUT_reg[4].CLK
WR => OUT_reg[3].CLK
WR => OUT_reg[2].CLK
WR => OUT_reg[1].CLK
WR => OUT_reg[0].CLK
WR => PATEND_reg.CLK
WR => ACICS_reg.CLK
WR => SIDIN_reg.CLK
WR => SICLK_reg.CLK
WR => SPI_CS_reg.CLK
WR => LCD_Data_reg[7].CLK
WR => LCD_Data_reg[6].CLK
WR => LCD_Data_reg[5].CLK
WR => LCD_Data_reg[4].CLK
WR => LCD_Data_reg[3].CLK
WR => LCD_Data_reg[2].CLK
WR => LCD_Data_reg[1].CLK
WR => LCD_Data_reg[0].CLK
WR => RS_reg.CLK
WR => E_reg.CLK
WR => LED_reg[7].CLK
WR => LED_reg[6].CLK
WR => LED_reg[5].CLK
WR => LED_reg[4].CLK
WR => LED_reg[3].CLK
WR => LED_reg[2].CLK
WR => LED_reg[1].CLK
WR => LED_reg[0].CLK
WR => BUZZER_reg.CLK
WR => SLWR~0.IN0
RD => DSP_Data~17.IN0
CS1 => DSP_Data~16.IN0
BUZZER <= BUZZER_reg.DB_MAX_OUTPUT_PORT_TYPE
Key[0] => LED_reg~8.IN1
Key[1] => LED_reg~9.IN1
Key[2] => LED_reg~10.IN1
Key[3] => LED_reg~11.IN1
Key[4] => LED_reg~12.IN1
Key[5] => LED_reg~13.IN1
Key[6] => LED_reg~14.IN1
Key[7] => LED_reg~15.IN1
LED[0] <= LED_reg[0].DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= LED_reg[1].DB_MAX_OUTPUT_PORT_TYPE
LED[2] <= LED_reg[2].DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= LED_reg[3].DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= LED_reg[4].DB_MAX_OUTPUT_PORT_TYPE
LED[5] <= LED_reg[5].DB_MAX_OUTPUT_PORT_TYPE
LED[6] <= LED_reg[6].DB_MAX_OUTPUT_PORT_TYPE
LED[7] <= LED_reg[7].DB_MAX_OUTPUT_PORT_TYPE
E <= E_reg.DB_MAX_OUTPUT_PORT_TYPE
RS <= RS_reg.DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[0] <= LCD_Data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[1] <= LCD_Data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[2] <= LCD_Data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[3] <= LCD_Data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[4] <= LCD_Data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[5] <= LCD_Data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[6] <= LCD_Data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
LCD_Data[7] <= LCD_Data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
PA0 => Selector7.IN7
PA1 => Selector6.IN7
SLOE <= SLOE~2.DB_MAX_OUTPUT_PORT_TYPE
PATEND <= PATEND_reg.DB_MAX_OUTPUT_PORT_TYPE
SLCS <= SLCS~0.DB_MAX_OUTPUT_PORT_TYPE
IFCLK => ~NO_FANOUT~
CLKOUT => ~NO_FANOUT~
SLRD <= SLRD~0.DB_MAX_OUTPUT_PORT_TYPE
SLWR <= SLWR~2.DB_MAX_OUTPUT_PORT_TYPE
FIFO_PROG => Selector5.IN5
FIFO_FULL => Selector6.IN8
FIFO_EMPTY => Selector7.IN8
SPI_CS <= SPI_CS_reg.DB_MAX_OUTPUT_PORT_TYPE
ACICS <= ACICS_reg.DB_MAX_OUTPUT_PORT_TYPE
SIDIN <= SIDIN_reg.DB_MAX_OUTPUT_PORT_TYPE
SICLK <= SICLK_reg.DB_MAX_OUTPUT_PORT_TYPE
IN[0] => Selector7.IN10
IN[1] => Selector6.IN10
IN[2] => Selector5.IN7
IN[3] => Selector4.IN5
IN[4] => Selector3.IN5
IN[5] => Selector2.IN4
IN[6] => Selector1.IN4
IN[7] => Selector0.IN4
IN[8] => Selector7.IN9
IN[9] => Selector6.IN9
IN[10] => Selector5.IN6
IN[11] => Selector4.IN4
IN[12] => Selector3.IN4
IN[13] => Selector2.IN3
IN[14] => Selector1.IN3
IN[15] => Selector0.IN3
OUT[0] <= OUT_reg[0].DB_MAX_OUTPUT_PORT_TYPE
OUT[1] <= OUT_reg[1].DB_MAX_OUTPUT_PORT_TYPE
OUT[2] <= OUT_reg[2].DB_MAX_OUTPUT_PORT_TYPE
OUT[3] <= OUT_reg[3].DB_MAX_OUTPUT_PORT_TYPE
OUT[4] <= OUT_reg[4].DB_MAX_OUTPUT_PORT_TYPE
OUT[5] <= OUT_reg[5].DB_MAX_OUTPUT_PORT_TYPE
OUT[6] <= OUT_reg[6].DB_MAX_OUTPUT_PORT_TYPE
OUT[7] <= OUT_reg[7].DB_MAX_OUTPUT_PORT_TYPE
OUT[8] <= OUT_reg[8].DB_MAX_OUTPUT_PORT_TYPE
OUT[9] <= OUT_reg[9].DB_MAX_OUTPUT_PORT_TYPE
OUT[10] <= OUT_reg[10].DB_MAX_OUTPUT_PORT_TYPE
OUT[11] <= OUT_reg[11].DB_MAX_OUTPUT_PORT_TYPE
OUT[12] <= OUT_reg[12].DB_MAX_OUTPUT_PORT_TYPE
OUT[13] <= OUT_reg[13].DB_MAX_OUTPUT_PORT_TYPE
OUT[14] <= OUT_reg[14].DB_MAX_OUTPUT_PORT_TYPE
OUT[15] <= OUT_reg[15].DB_MAX_OUTPUT_PORT_TYPE
INT1 <= INT1_reg~0.DB_MAX_OUTPUT_PORT_TYPE
NMI <= NMI_reg~0.DB_MAX_OUTPUT_PORT_TYPE
EXINT[0] => EXINT_reg[0].DATAIN
EXINT[0] => Equal0.IN9
EXINT[1] => EXINT_reg[1].DATAIN
EXINT[1] => Equal0.IN8
EXINT[2] => EXINT_reg[2].DATAIN
EXINT[2] => Equal0.IN7
EXINT[3] => EXINT_reg[3].DATAIN
EXINT[3] => Equal0.IN6
EXINT[4] => EXINT_reg[4].DATAIN
EXINT[4] => Equal0.IN5
NMI1 => NMI1_reg.DATAIN
NMI1 => always4~1.IN0
NMI2 => NMI2_reg.DATAIN
NMI2 => always4~0.IN0
TXB => TXB1~0.IN0
TXB1 <= TXB1~0.DB_MAX_OUTPUT_PORT_TYPE
RXB => ~NO_FANOUT~
CANRX <= CANRX_1.DB_MAX_OUTPUT_PORT_TYPE
CANTX => CANTX_1.DATAIN
CANRX_1 => CANRX.DATAIN
CANTX_1 <= CANTX.DB_MAX_OUTPUT_PORT_TYPE