?? cpld_qq2812.map.rpt
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Analysis & Synthesis report for CPLD_QQ2812
Sat Mar 21 17:16:08 2009
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. Analysis & Synthesis Messages
9. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Mar 21 17:16:08 2009 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name ; CPLD_QQ2812 ;
; Top-level Entity Name ; CPLD_QQ2812 ;
; Family ; MAX3000A ;
; Total macrocells ; 72 ;
; Total pins ; 108 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------+------------------+---------------+
; Device ; EPM3256AFC256-10 ; ;
; Top-level entity name ; CPLD_QQ2812 ; CPLD_QQ2812 ;
; Family name ; MAX3000A ; Stratix II ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Auto ; Auto ;
; Ignore SOFT Buffers ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell ; 100 ; 100 ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+------------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------+
; CPLD_QQ2812.v ; yes ; User Verilog HDL File ; E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.v ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 72 ;
; Total registers ; 48 ;
; I/O pins ; 108 ;
; Parallel expanders ; 7 ;
; Maximum fan-out node ; DSP_Add[0] ;
; Maximum fan-out ; 60 ;
; Total fan-out ; 668 ;
; Average fan-out ; 3.71 ;
+----------------------+----------------------+
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |CPLD_QQ2812 ; 72 ; 108 ; |CPLD_QQ2812 ; work ;
+----------------------------+------------+------+---------------------+--------------+
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; EXINT_reg[0] ; Equal0 ; yes ;
; NMI1_reg ; always4~2 ; yes ;
; EXINT_reg[1] ; Equal0 ; yes ;
; NMI2_reg ; always4~2 ; yes ;
; EXINT_reg[2] ; Equal0 ; yes ;
; EXINT_reg[3] ; Equal0 ; yes ;
; EXINT_reg[4] ; Equal0 ; yes ;
; Number of user-specified and inferred latches = 7 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
Info: Processing started: Sat Mar 21 17:16:05 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CPLD_QQ2812 -c CPLD_QQ2812
Info: Found 1 design units, including 1 entities, in source file CPLD_QQ2812.v
Info: Found entity 1: CPLD_QQ2812
Info: Elaborating entity "CPLD_QQ2812" for the top level hierarchy
Warning (10240): Verilog HDL Always Construct warning at CPLD_QQ2812.v(170): inferring latch(es) for variable "EXINT_reg", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at CPLD_QQ2812.v(183): inferring latch(es) for variable "NMI1_reg", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at CPLD_QQ2812.v(183): inferring latch(es) for variable "NMI2_reg", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(197): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(198): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(199): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CPLD_QQ2812.v(200): truncated value with size 32 to match size of target (1)
Info (10041): Inferred latch for "NMI2_reg" at CPLD_QQ2812.v(193)
Info (10041): Inferred latch for "NMI1_reg" at CPLD_QQ2812.v(193)
Info (10041): Inferred latch for "EXINT_reg[0]" at CPLD_QQ2812.v(179)
Info (10041): Inferred latch for "EXINT_reg[1]" at CPLD_QQ2812.v(179)
Info (10041): Inferred latch for "EXINT_reg[2]" at CPLD_QQ2812.v(179)
Info (10041): Inferred latch for "EXINT_reg[3]" at CPLD_QQ2812.v(179)
Info (10041): Inferred latch for "EXINT_reg[4]" at CPLD_QQ2812.v(179)
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "WR" to global clock signal
Info: Promoted clock signal driven by pin "RD" to global clock signal
Warning: Design contains 3 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "IFCLK"
Warning (15610): No output dependent on input pin "CLKOUT"
Warning (15610): No output dependent on input pin "RXB"
Info: Implemented 180 device resources after synthesis - the final resource count might be different
Info: Implemented 51 input pins
Info: Implemented 49 output pins
Info: Implemented 8 bidirectional pins
Info: Implemented 72 macrocells
Info: Generated suppressed messages file E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
Info: Peak virtual memory: 172 megabytes
Info: Processing ended: Sat Mar 21 17:16:09 2009
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/CODE/CODEQQ2812/EX22_CPLD_QQ2812/CPLD_QQ2812.map.smsg.
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