#define T_MCR_MR0I          (0x00000001)#define T_MCR_MR0R          (0x00000002)#define T_MCR_MR0S          (0x00000004)#define T_MCR_MR1I          (0x00000008)#define T_MCR_MR1R          (0x00000010)#define T_MCR_MR1S          (0x00000020)#define T_MCR_MR2I          (0x00000040)#define T_MCR_MR2R          (0x00000080)#define T_MCR_MR2S          (0x00000100)#define T_MCR_MR3I          (0x00000200)#define T_MCR_MR3R          (0x00000400)#define T_MCR_MR3S          (0x00000800)#define T_CCR_CAP0RE        (0x00000001)#define T_CCR_CAP0FE        (0x00000002)#define T_CCR_CAP0I         (0x00000004)#define T_CCR_CAP1RE        (0x00000008)#define T_CCR_CAP1FE        (0x00000010)#define T_CCR_CAP1I         (0x00000020)#define T_CCR_CAP2RE        (0x00000040)#define T_CCR_CAP2FE        (0x00000080)#define T_CCR_CAP2I         (0x00000100)#define T_CCR_CAP3RE        (0x00000200)#define T_CCR_CAP3FE        (0x00000400)#define T_CCR_CAP3I         (0x00000800)#define T_EMR_EM0           (0x00000001)#define T_EMR_EM1           (0x00000002)#define T_EMR_EM2           (0x00000004)#define T_EMR_EM3           (0x00000008)#define T_EMR_EMC0_NONE     (0x00000000)#define T_EMR_EMC0_CLEAR    (0x00000010)#define T_EMR_EMC0_SET      (0x00000020)#define T_EMR_EMC0_TOGGLE   (0x00000030)#define T_EMR_EMC0_MASK     (0x00000030)#define T_EMR_EMC1_NONE     (0x00000000)#define T_EMR_EMC1_CLEAR    (0x00000040)#define T_EMR_EMC1_SET      (0x00000080)#define T_EMR_EMC1_TOGGLE   (0x000000c0)#define T_EMR_EMC1_MASK     (0x000000c0)#define T_EMR_EMC2_NONE     (0x00000000)#define T_EMR_EMC2_CLEAR    (0x00000100)#define T_EMR_EMC2_SET      (0x00000200)#define T_EMR_EMC2_TOGGLE   (0x00000300)#define T_EMR_EMC2_MASK     (0x00000300)#define T_EMR_EMC3_NONE     (0x00000000)#define T_EMR_EMC3_CLEAR    (0x00000400)#define T_EMR_EMC3_SET      (0x00000800)#define T_EMR_EMC3_TOGGLE   (0x00000c00)#define T_EMR_EMC3_MASK     (0x00000c00)/*################################################################################ ADC##############################################################################*/#define AD0_CR              (*(pREG32 (0xe0034000)))#define AD0_GDR             (*(pREG32 (0xe0034004)))#define AD0_STAT            (*(pREG32 (0xe0034030)))#define AD0_GSR             (*(pREG32 (0xe0034008)))#define AD0_INTEN           (*(pREG32 (0xe003400c)))#define AD0_DR0             (*(pREG32 (0xe0034010)))#define AD0_DR1             (*(pREG32 (0xe0034014)))#define AD0_DR2             (*(pREG32 (0xe0034018)))#define AD0_DR3             (*(pREG32 (0xe003401c)))#define AD0_DR4             (*(pREG32 (0xe0034020)))#define AD0_DR5             (*(pREG32 (0xe0034024)))#define AD0_DR6             (*(pREG32 (0xe0034028)))#define AD0_DR7             (*(pREG32 (0xe003402c)))#define AD1_CR              (*(pREG32 (0xe0060000)))#define AD1_GDR             (*(pREG32 (0xe0060004)))#define AD1_STAT            (*(pREG32 (0xe0060030)))#define AD1_GSR             (*(pREG32 (0xe0030008)))#define AD1_INTEN           (*(pREG32 (0xe006000c)))#define AD1_DR0             (*(pREG32 (0xe0060010)))#define AD1_DR1             (*(pREG32 (0xe0060014)))#define AD1_DR2             (*(pREG32 (0xe0060018)))#define AD1_DR3             (*(pREG32 (0xe006001c)))#define AD1_DR4             (*(pREG32 (0xe0060020)))#define AD1_DR5             (*(pREG32 (0xe0060024)))#define AD1_DR6             (*(pREG32 (0xe0060028)))#define AD1_DR7             (*(pREG32 (0xe006002c)))#define AD_CR_SEL0          (0x00000001)#define AD_CR_SEL1          (0x00000002)#define AD_CR_SEL2          (0x00000004)#define AD_CR_SEL3          (0x00000008)#define AD_CR_SEL4          (0x00000010)#define AD_CR_SEL5          (0x00000020)#define AD_CR_SEL6          (0x00000040)#define AD_CR_SEL7          (0x00000080)#define AD_CR_SELMASK       (0x000000ff)#define AD_CR_CLKDIV        (0x0000ff00)#define AD_CR_CLKDIVMASK    (0x0000ff00)#define AD_CR_CLKDIVSHIFT   (8)#define AD_CR_BURST         (0x00010000)#define AD_CR_CLKS10        (0x00000000)#define AD_CR_CLKS9         (0x00020000)#define AD_CR_CLKS8         (0x00040000)#define AD_CR_CLKS7         (0x00060000)#define AD_CR_CLKS6         (0x00080000)#define AD_CR_CLKS5         (0x000a0000)#define AD_CR_CLKS4         (0x000c0000)#define AD_CR_CLKS3         (0x000e0000)#define AD_CR_PDN           (0x00200000)#define AD_CR_START_NONE    (0x00000000)#define AD_CR_START_NOW     (0x01000000)#define AD_CR_START_P016    (0x02000000)#define AD_CR_START_P022    (0x03000000)#define AD_CR_START_MAT01   (0x04000000)#define AD_CR_START_MAT03   (0x05000000)#define AD_CR_START_MAT10   (0x06000000)#define AD_CR_START_MAT11   (0x07000000)#define AD_CR_START_MASK    (0x07000000)#define AD_CR_EDGE          (0x08000000)#define AD_CR_MASK          (0x0f2fffff)#define AD_GDR_RESULT       (0x0000ffc0)#define AD_GDR_CHN          (0x07000000)#define AD_GDR_CHNMASK      (0x07000000)#define AD_GDR_CHNSHIFT     (24)#define AD_GDR_OVERRUN      (0x40000000)#define AD_GDR_DONE         (0x80000000)#define AD_GDR_MASK         (0xc700ffc0)#define AD_GSR_BURST        (0x00010000)#define AD_GSR_START_NONE   (0x00000000)#define AD_GSR_START_NOW    (0x01000000)#define AD_GSR_START_P016   (0x02000000)#define AD_GSR_START_P022   (0x03000000)#define AD_GSR_START_MAT01  (0x04000000)#define AD_GSR_START_MAT03  (0x05000000)#define AD_GSR_START_MAT10  (0x06000000)#define AD_GSR_START_MAT11  (0x07000000)#define AD_GSR_EDGE         (0x08000000)#define AD_GSR_MASK         (0x0f010000)#define AD_STAT_RSVD        (0x00000001)#define AD_STAT_DONE0       (0x00000001)#define AD_STAT_DONE1       (0x00000002)#define AD_STAT_DONE2       (0x00000004)#define AD_STAT_DONE3       (0x00000008)#define AD_STAT_DONE4       (0x00000010)#define AD_STAT_DONE5       (0x00000020)#define AD_STAT_DONE6       (0x00000040)#define AD_STAT_DONE7       (0x00000080)#define AD_STAT_OVERRUN0    (0x00000100)#define AD_STAT_OVERRUN1    (0x00000200)#define AD_STAT_OVERRUN2    (0x00000400)#define AD_STAT_OVERRUN3    (0x00000800)#define AD_STAT_OVERRUN4    (0x00001000)#define AD_STAT_OVERRUN5    (0x00002000)#define AD_STAT_OVERRUN6    (0x00004000)#define AD_STAT_OVERRUN7    (0x00008000)#define AD_STAT_ADINT       (0x00010000)#define AD_STAT_MASK        (0x0001ffff)#define AD_INTEN_AD0        (0x00000001)#define AD_INTEN_AD1        (0x00000002)#define AD_INTEN_AD2        (0x00000004)#define AD_INTEN_AD3        (0x00000008)#define AD_INTEN_AD4        (0x00000010)#define AD_INTEN_AD5        (0x00000020)#define AD_INTEN_AD6        (0x00000040)#define AD_INTEN_AD7        (0x00000080)#define AD_INTEN_DONE       (0x00000100)#define AD_INTEN_MASK       (0x000001ff)#define AD_DR_RESULT        (0x0000ffc0)#define AD_DR_RESULTMASK    (0x0000ffc0)#define AD_DR_RESULTSHIFT   (6)#define AD_DR_OVERRUN       (0x40000000)#define AD_DR_DONE          (0x80000000)#define AD_DR_MASK          (0xc000ffc0)/*################################################################################ DAC##############################################################################*/#define DAC_CR            (*(pREG32 (0xe006c000)))#define DAC_CR_VALUE      (0x0000ffc0)#define DAC_CR_VALUEMASK  (0x0000ffc0)#define DAC_CR_VALUESHIFT (6)#define DAC_CR_BIAS       (0x00010000)#define DAC_CR_MASK       (0x0001ffc0)/*################################################################################ PWM##############################################################################*/#define PWM_IR            (*(pREG32 (0xe0014000)))#define PWM_TCR           (*(pREG32 (0xe0014004)))#define PWM_TC            (*(pREG32 (0xe0014008)))#define PWM_PR            (*(pREG32 (0xe001400c)))#define PWM_PC            (*(pREG32 (0xe0014010)))#define PWM_MCR           (*(pREG32 (0xe0014014)))#define PWM_MR0           (*(pREG32 (0xe0014018)))#define PWM_MR1           (*(pREG32 (0xe001401c)))#define PWM_MR2           (*(pREG32 (0xe0014020)))#define PWM_MR3           (*(pREG32 (0xe0014024)))#define PWM_MR4           (*(pREG32 (0xe0014040)))#define PWM_MR5           (*(pREG32 (0xe0014044)))#define PWM_MR6           (*(pREG32 (0xe0014048)))#define PWM_EMR           (*(pREG32 (0xe001403c)))#define PWM_PCR           (*(pREG32 (0xe001404c)))#define PWM_LER           (*(pREG32 (0xe0014050)))#define PWM_IR_MR0        ((unsigned int) 0x00000001)#define PWM_IR_MR1        ((unsigned int) 0x00000002)#define PWM_IR_MR2        ((unsigned int) 0x00000004)#define PWM_IR_MR3        ((unsigned int) 0x00000008)#define PWM_IR_MR4        ((unsigned int) 0x00000100)#define PWM_IR_MR5        ((unsigned int) 0x00000200)#define PWM_IR_MR6        ((unsigned int) 0x00000400)#define PWM_IR_MASK       ((unsigned int) 0x0000070f)#define PWM_TCR_CE        ((unsigned int) 0x00000001)#define PWM_TCR_CR        ((unsigned int) 0x00000002)#define PWM_TCR_PWME      ((unsigned int) 0x00000008)#define PWM_TCR_MASK      ((unsigned int) 0x0000000b)#define PWM_MCR_MR0I      ((unsigned int) 0x00000001)#define PWM_MCR_MR0R      ((unsigned int) 0x00000002)#define PWM_MCR_MR0S      ((unsigned int) 0x00000004)#define PWM_MCR_MR1I      ((unsigned int) 0x00000008)#define PWM_MCR_MR1R      ((unsigned int) 0x00000010)#define PWM_MCR_MR1S      ((unsigned int) 0x00000020)#define PWM_MCR_MR2I      ((unsigned int) 0x00000040)#define PWM_MCR_MR2R      ((unsigned int) 0x00000080)#define PWM_MCR_MR2S      ((unsigned int) 0x00000100)#define PWM_MCR_MR3I      ((unsigned int) 0x00000200)#define PWM_MCR_MR3R      ((unsigned int) 0x00000400)#define PWM_MCR_MR3S      ((unsigned int) 0x00000800)#define PWM_MCR_MR4I      ((unsigned int) 0x00001000)#define PWM_MCR_MR4R      ((unsigned int) 0x00002000)#define PWM_MCR_MR4S      ((unsigned int) 0x00004000)#define PWM_MCR_MR5I      ((unsigned int) 0x00008000)#define PWM_MCR_MR5R      ((unsigned int) 0x00010000)#define PWM_MCR_MR5S      ((unsigned int) 0x00020000)#define PWM_MCR_MR6I      ((unsigned int) 0x00040000)#define PWM_MCR_MR6R      ((unsigned int) 0x00080000)#define PWM_MCR_MR6S      ((unsigned int) 0x00100000)#define PWM_MCR_MASK      ((unsigned int) 0x001fffff)#define PWM_PCR_SEL2      ((unsigned int) 0x00000004)#define PWM_PCR_SEL3      ((unsigned int) 0x00000008)#define PWM_PCR_SEL4      ((unsigned int) 0x00000010)#define PWM_PCR_SEL5      ((unsigned int) 0x00000020)#define PWM_PCR_SEL6      ((unsigned int) 0x00000040)#define PWM_PCR_SEL_MASK  ((unsigned int) 0x0000007c)#define PWM_PCR_ENA1      ((unsigned int) 0x00000200)#define PWM_PCR_ENA2      ((unsigned int) 0x00000400)#define PWM_PCR_ENA3      ((unsigned int) 0x00000800)#define PWM_PCR_ENA4      ((unsigned int) 0x00001000)#define PWM_PCR_ENA5      ((unsigned int) 0x00002000)#define PWM_PCR_ENA6      ((unsigned int) 0x00004000)#define PWM_PCR_ENA_MASK  ((unsigned int) 0x00007d00)#define PWM_PCR_MASK      ((unsigned int) 0x00007d00)#define PWM_LER_M0L       ((unsigned int) 0x00000001)#define PWM_LER_M1L       ((unsigned int) 0x00000002)#define PWM_LER_M2L       ((unsigned int) 0x00000004)#define PWM_LER_M3L       ((unsigned int) 0x00000008)#define PWM_LER_M4L       ((unsigned int) 0x00000010)#define PWM_LER_M5L       ((unsigned int) 0x00000020)#define PWM_LER_M6L       ((unsigned int) 0x00000040)#define PWM_LER_MASK      ((unsigned int) 0x0000007f)/*################################################################################ RTC##############################################################################*/#define RTC_ILR         (*(pREG32 (0xe0024000)))#define RTC_CTC         (*(pREG32 (0xe0024004)))#define RTC_CCR         (*(pREG32 (0xe0024008)))  #define RTC_CIIR        (*(pREG32 (0xe002400c)))#define RTC_AMR         (*(pREG32 (0xe0024010)))#define RTC_CTIME0      (*(pREG32 (0xe0024014)))#define RTC_CTIME1      (*(pREG32 (0xe0024018)))#define RTC_CTIME2      (*(pREG32 (0xe002401c)))#define RTC_SEC         (*(pREG32 (0xe0024020)))#define RTC_MIN         (*(pREG32 (0xe0024024)))#define RTC_HOUR        (*(pREG32 (0xe0024028)))#define RTC_DOM         (*(pREG32 (0xe002402c)))#define RTC_DOW         (*(pREG32 (0xe0024030)))#define RTC_DOY         (*(pREG32 (0xe0024034)))#define RTC_MONTH       (*(pREG32 (0xe0024038)))#define RTC_YEAR        (*(pREG32 (0xe002403c)))#define RTC_ALSEC       (*(pREG32 (0xe0024060)))#define RTC_ALMIN       (*(pREG32 (0xe0024064)))#define RTC_ALHOUR      (*(pREG32 (0xe0024068)))#define RTC_ALDOM       (*(pREG32 (0xe002406c)))#define RTC_ALDOW       (*(pREG32 (0xe0024070)))#define RTC_ALDOY       (*(pREG32 (0xe0024074)))#define RTC_ALMON       (*(pREG32 (0xe0024078)))#define RTC_ALYEAR      (*(pREG32 (0xe002407c)))#define RTC_PREINT      (*(pREG32 (0xe0024080)))#define RTC_PREFRAC     (*(pREG32 (0xe0024084)))#define RTC_ILR_RTCCIF  (0x00000001)#define RTC_ILR_RTCALF  (0x00000002)#define RTC_ILR_MASK    (0x00000003)